Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
ID
813652
Date
4/14/2025
Public
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. TX PCS Interface to User Logic
6.4. RX PCS Interface to User Logic
6.5. GTS Transceivers Signals
6.6. GTS Transceiver Reconfiguration Signals
6.7. Avalon® Memory-Mapped Management Interface
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
6.10. Clocks
6.11. Flow Control Interface
6.12. GTS Reset Sequencer Intel® FPGA IP
6.2. RX MAC Interface to User Logic
The RX MAC interface signals are available only in MAC, PCS, and PMA mode. The RX MAC provides an Avalon® streaming interface to the FPGA fabric. The datapath comprises 2, 64-bit words. A valid FCS for a packet results in l2_rx_error bit 1 being low when l2_rx_endofpacket is high. An FCS violation is indicated when l2_rx_error bit 1 is high when l2_rx_endofpacket is high.
Signal |
Direction |
Width |
Description |
---|---|---|---|
clk_rxmac | Output | 1 | Clock for the RX MAC. Generated from the incoming data and is an output from the core (312.5 MHz). |
l2_rx_data | Output | 128 | Data output from the MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order. The IP reverses the byte order to meet the requirements of the Ethernet standard. |
l2_rx_preamble | Output | 64 | Received preamble data. Available when you select PREAMBLE PASS-THROUGH mode. Valid when l2_rx_startofpacket is asserted. |
l2_rx_valid | Output | 1 | When asserted, indicates that l2_rx_data[127:0] is driving data. When this signal is low, the IP ignores l2_rx_data, l2_rx_startofpacket, l2_rx_endofpacket, l2_rx_empty, and l2_rx_error. |
l2_rx_startofpacket | Output | 1 | When asserted, indicates the first byte of a frame. |
l2_rx_endofpacket | Output | 1 | When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position. |
l2_rx_empty | Output | 4 | Specifies the number of empty bytes when l2_rx_endofpacket is asserted. The packet can end at any byte position. The empty bytes are the low-order bytes. |
l2_rx_error | Output | 6 | When asserted in the same cycle as l2_rx_endofpacket, indicates the current packet should be treated as an error packet. It is valid when l2_rx_endofpacket is high.
|
l2_rxstatus_valid | Output | 1 | When asserted, indicates that l2_rxstatus_data is driving valid data. |
l2_rxstatus_data[39:0] | Output | 40 | Specifies information about the received frame.
|