Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
ID
813652
Date
4/14/2025
Public
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. TX PCS Interface to User Logic
6.4. RX PCS Interface to User Logic
6.5. GTS Transceivers Signals
6.6. GTS Transceiver Reconfiguration Signals
6.7. Avalon® Memory-Mapped Management Interface
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
6.10. Clocks
6.11. Flow Control Interface
6.12. GTS Reset Sequencer Intel® FPGA IP
6.11. Flow Control Interface
These signals are accessible only in MAC, PCS, and PMA mode.
Signal Name |
Direction |
Width |
Description |
---|---|---|---|
pause_insert_tx0 |
Input | QN |
These signals are available only if Pause or PFC flow control support is synthesized. Indicates the MAC whether a XON or XOFF Pause or PFC flow control frame should be sent.
The request for XON/XOFF flow control frame transmission can be done in either 1 or 2-bit request mode (see pause_insert_tx1). 1-bit mode request model:
The following encoding is defined:
2-bit mode request model: Represents the lower bit. Only takes effect when the CSR of 2-bit Flow Control Request mode selects "Signal". The following encoding is defined:
|
pause_insert_tx1 | Input | QN | Used in conjunction with pause_insert_tx0 to form a 2-bit request for XON/XOFF flow control frame transmission. This represents the upper bit of the 2-bit control. |
pause_receive_rx | Output | QN | Asserted to indicate an RX pause signal match. The IP asserts bit [n] of this signal when it receives a pause request with an address match, to signal the TX MAC to throttle its transmissions from priority queue [n] on the Ethernet link. |