Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

6.1. TX MAC Interface to User Logic

The Ready Latency could be configured to 0 or 3 for easier timing closure. The user interface for the TX MAC is an Avalon® streaming interface. The data is 128 bits wide, consisting of 2 words of 64 bits each. Packets with SOP and EOP in the same word are ignored; the minimum supported packet size is 9 bytes. If l2_tx_startofpacket is set, it implies that the MSB of l2_tx_data has the start of packet. The l2_tx_empty vector indicates how many bytes in the last transfer are not valid; it only has meaning when l2_tx_endofpacket is asserted. Once a start of packet is seen on the bus, all data until l2_tx_endofpacket is assumed to be part of the packet. The packet ends with l2_tx_endofpacket.
Table 16.   Avalon® Streaming TX MAC Interface SignalsAll interface signals are clocked by the clk_txmac clock. The value you specify for Ready latency in the Low Latency 40G Ethernet IP parameter editor for Agilex™ 5 devices is the Avalon® streaming interface readyLatency value on this interface.

Signal

Direction

Width

Description

clk_txmac Output 1

The TX clock for the IP is clk_txmac. The frequency of this clock is 312.5  MHz. This is derived from the tx_clkout[0] of the PMA.

l2_tx_data Input 128

Data input to MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order.
l2_tx_preamble Input 64

User preamble data. Available when you turn on Enable preamble passthrough mode.

User logic drives the custom preamble data when l2_tx_startofpacket is asserted.

The l2_tx_preamble [63:56] has to be 8’hfb.

l2_tx_valid Input 1 When asserted, indicates valid data.
l2_tx_startofpacket Input 1 When asserted, indicates the first byte of a frame.
l2_tx_endofpacket Input 1 When asserted, indicates the end of a packet.
l2_tx_empty Input 4 Specifies the number of empty bytes when l2_tx_endofpacket is asserted.
l2_tx_ready Output 1 When asserted, indicates that the MAC can accept the data. The data is processed only when l2_tx_ready is asserted.
l2_tx_error Input 1 A high on this signal aligned with a valid EOP indicates that the current packet needs to be treated as error packet
l2_txstatus_valid Output 1 When asserted, indicates that l2_txstatus_data is driving valid data.
l2_txstatus_data Output 40

Specifies information about the transmit frame.
l2_txstatus_error Output 7

Specifies the error type in the transmit frame.
Figure 14.  Client to MAC Avalon® Streaming Interface l2_tx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l2_tx_data[127:120] , 0xabe4233 . . . in this timing diagram. The ready latency is 0 in this example.
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