Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813652
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency 40G Ethernet Intel® FPGA IP 2. Low Latency 40G Ethernet Intel® FPGA IP Parameters 3. Getting Started 4. Functional Description 5. Clocking and Reset Requirements 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs 9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. About the Low Latency 40G Ethernet Intel® FPGA IP x
1.1. Low Latency 40G Ethernet Intel® FPGA IP Supported Features 1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.3. Resource Utilization 1.4. Release Information
1.2. Low Latency 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.2.1. Low Latency 40G Ethernet Intel® FPGA IP Device Family Support 1.2.2. Low Latency 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Introduction to Intel® FPGA IP 3.2. Installing and Licensing Intel® FPGA IPs 3.3. Specifying the IP Parameters and Options 3.4. Simulating the IP 3.5. Generated File Structure 3.6. Integrating Your IP in Your Design 3.7. Testbench 3.8. Compiling the Full Design and Programming the FPGA
3.6. Integrating Your IP in Your Design x
3.6.1. Pin Assignments 3.6.2. Placement Settings
3.7. Testbench x
3.7.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency 40G Ethernet Intel® FPGA IP Functional Description 4.2. GTS Transceiver Configuration 4.3. TX MAC Datapath 4.4. RX MAC Datapath 4.5. Flow Control 4.6. Frame Status Checking 4.7. Link Fault Signaling Interface
4.3. TX MAC Datapath x
4.3.1. Preamble Pass-through/Insertion 4.3.2. Padding Bytes Insertion 4.3.3. Deficit Idle Count 4.3.4. TX CRC Insertion/Passthrough 4.3.5. TX Avalon® Streaming Filter 4.3.6. TX PCS 4.3.7. PMA
4.4. RX MAC Datapath x
4.4.1. RX Preamble Pass-through or Removal 4.4.2. RX CRC Checking and Dynamic Option to Forward 4.4.3. Strict SFD/Preamble Checking 4.4.4. RX PCS Functional Description
4.5. Flow Control x
4.5.1. TX Pause/PFC Flow Control Transmission 4.5.2. XON/XOFF Pause Frames
4.6. Frame Status Checking x
4.6.1. Frame Type Checking 4.6.2. Length Checking
5. Clocking and Reset Requirements x
5.1. Reset Requirements
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. GTS Transceivers Signals 6.4. GTS Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface 6.10. GTS Reset Sequencer Intel® FPGA IP
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control 7.5. Statistics Counters 7.6. Shadow Register
1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

4.6. Frame Status Checking

The IP checks the frame transmitted, frames received, and report the status information on the TX and RX interfaces:
Table 13.  TX Interface
Signal Direction Width Description
l2_txstatus_valid Out 1 When asserted, this signal qualifies l2_txstatus_data and l2_txstatus_error.
l2_txstatus_data Out 40

Contains information about the transmit frame.

  • Bits 0 to 15: Payload length
  • Bits 16 to 31: Frame length (from first byte of destination address to last byte of FCS)
  • Bit 32: Indicates a stacked VLAN frame
  • Bit 33: Indicates a VLAN frame.
  • Bit 34: Indicates a control frame.
  • Bit 35: Indicates a pause frame.
  • Bit 36: Indicates a broadcast frame.
  • Bit 37: Indicates a multicast frame.
  • Bit 38: Indicates a unicast frame.
  • Bit 39: Indicates a PFC frame.
l2_txstatus_error Out 7

When set to 1, the respective bit indicates the following error type in the transmit frame.

  • Bit 0: Unused
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error
  • Bit 3 to 6: Unused
Table 14.  RX Interface
Signal Direction Width Description
l2_rxstatus_valid Out 1 When asserted, this signal qualifies l<x>_rxstatus_data.
l2_rxstatus_data Out 40

Contains information about the transmit frame.

  • Bits 0 to 15: Payload length
  • Bits 16 to 31: Frame length (from first byte of destination address to last byte of FCS)
  • Bit 32: Indicates a stacked VLAN frame
  • Bit 33: Indicates a VLAN frame.
  • Bit 34: Indicates a control frame.
  • Bit 35: Indicates a pause frame.
  • Bit 36: Indicates a broadcast frame.
  • Bit 37: Indicates a multicast frame.
  • Bit 38: Indicates a unicast frame.
  • Bit 39: Indicates a PFC frame.
l2_rxstatus_error Out  

Bit 0: PHY Error or malformed packet error.

  • Bit 1: CRC Error. The computed CRC value differs from the received CRC value.
  • Bit 2: Undersize error. The frame size is less than 64 bytes.
  • Bit 3: Oversize Error. The frame size is more than MAX_RX_SIZE_CONFIG register value.
  • Bit 4: Length Error. The actual frame payload length differs from the length/type field.
  • Bit 5: N/A.

This signal is aligned with rx_endofpacket.


Section Content
Frame Type Checking
Length Checking

Level Two Title