Cyclone® V GT FPGA Development Kit User Guide

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ID 792833
Date 12/12/2025
Public
Document Table of Contents
Document Table of Contents x
1. Kit Features 2. Getting Started 3. Software Installation 4. Development Board Setup 5. Board Update Portal 6. Board Test System 7. Document Revision History for the Cyclone® V GT FPGA Development Kit User Guide A. Programming the Flash Memory Device B. Safety and Regulatory Compliance Information
1. Kit Features x
1.1. Hardware 1.2. Software
1.2. Software x
1.2.1. Quartus® Prime Software 1.2.2. Cyclone® V GT FPGA Development Kit Installer
2. Getting Started x
2.1. Before You Begin 2.2. Inspecting the Boards 2.3. References for Getting Started
2.2. Inspecting the Boards x
2.2.1. Handling the DIP Switches
3. Software Installation x
3.1. Installing the Quartus® Prime Standard Edition Software 3.2. Installing the Development Kit 3.3. Installing the Intel® FPGA Download Cable II Driver
4. Development Board Setup x
4.1. Setting Up the Board 4.2. Factory Default Switch and Jumper Settings 4.3. Configuring the MAX® V Device to Program EPCQ 4.4. Restoring the MAX® V CPLD to the Factory Settings 4.5. Restoring the Flash Device to the Factory Settings 4.6. Configuring the FPGA Using the Quartus® Prime Programmer
5. Board Update Portal x
5.1. Connecting to the Board Update Portal Web Page 5.2. Using the Board Update Portal to Write User Designs
6. Board Test System x
6.1. Preparing to Run the Board Test System 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. The Power Monitor 6.5. The Clock Control
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The DDR3x40 and DDR3x64 Tabs 6.3.6. The HSMA Tab 6.3.7. The HSMB Tab
6.3.2. The System Info Tab x
6.3.2.1. Power Tree 6.3.2.2. Power Monitor 6.3.2.3. Board Information 6.3.2.4. MAX® V Registers 6.3.2.5. JTAG Chain
6.3.3. The GPIO Tab x
6.3.3.1. Character LCD and Display 6.3.3.2. User DIP Switches 6.3.3.3. User LEDs 6.3.3.4. Push Buttons
6.3.4. The Flash Tab x
6.3.4.1. Read and Start Address 6.3.4.2. Range 6.3.4.3. Write 6.3.4.4. CFI Query 6.3.4.5. Reset 6.3.4.6. Erase 6.3.4.7. Flash Memory Table and Flash Memory Map
6.3.5. The DDR3x40 and DDR3x64 Tabs x
6.3.5.1. Start 6.3.5.2. Stop 6.3.5.3. Performance Indicators 6.3.5.4. Error Control 6.3.5.5. Number of Addresses to Write and Read
6.3.6. The HSMA Tab x
6.3.6.1. Start, Stop 6.3.6.2. XCRV, LVDS, CMOS
6.3.7. The HSMB Tab x
6.3.7.1. Start, Stop 6.3.7.2. XCRV and CMOS
6.4. The Power Monitor x
6.4.1. Power Monitor Features 6.4.2. Power Monitor Controls
6.4.2. Power Monitor Controls x
6.4.2.1. General Information 6.4.2.2. Power Information 6.4.2.3. Power Graph 6.4.2.4. Graph Settings 6.4.2.5. Reset
6.5. The Clock Control x
6.5.1. Clock Control Features 6.5.2. Clock Control Controls
6.5.2. Clock Control Controls x
6.5.2.1. Serial Port Registers 6.5.2.2. fXTAL 6.5.2.3. Target Frequency 6.5.2.4. Clear 6.5.2.5. Set New Frequency
A. Programming the Flash Memory Device x
A.1. CFI Flash Memory Map A.2. Preparing Design Files for Flash Programming A.3. Creating Flash Files Using the Nios® II EDS A.4. Converting Additional Files A.5. Programming Flash Memory Using the Nios® II EDS A.6. Programming Flash Memory Using the Board Update Portal
B. Safety and Regulatory Compliance Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Kit Features
2. Getting Started
3. Software Installation
4. Development Board Setup
5. Board Update Portal
6. Board Test System
7. Document Revision History for the Cyclone® V GT FPGA Development Kit User Guide
A. Programming the Flash Memory Device
B. Safety and Regulatory Compliance Information

1.2.1. Quartus® Prime Software

Your kit includes a license for the Development Kit Edition (DKE) of the Quartus® Prime software (Windows* platform only). For one year, this license entitles you to most of the features of the Subscription Edition (excluding the IP Base Suite).

After tone the DKE license will not be valid and you will not be permitted to use this version of the Quartus® Prime software. To continue using the Quartus® Prime software, you should download the free Quartus® Prime Web edition or purchase a subscription to Quartus® Prime software. For more information, refer to the Quartus® Prime Design Software page of the Altera website.

The Quartus® Prime Development Kit Edition (DKE) software includes the following items:

  • Quartus® Prime software—The Quartus® Prime software, including the Platform Designer (Standard) system integration tool, provides a comprehensive environment for network on a chip (NoC) design. The Quartus® Prime software integrates into nearly any design environment and provides interfaces to industry-standard EDA tools.
  • Altera IP Library—A library that contains Altera IP functions. You can evaluate Altera IP functions by using the Altera IP Evaluation Mode feature to do the following:
    • Simulate behavior of an Altera IP function within your system.
    • Verify functionality of your design, and quickly and easily evaluate its size and speed.
    • Generate time-limited device programming files for designs that include Altera IP functions.
    • Program a device and verify your design in hardware.

The Altera IP Evaluation Mode hardware evaluation feature is an evaluation tool for prototyping only. You must purchase a license to use an Altera IP function in production.

For more information about the Altera IP Evaluation Mode, refer to AN 320: Using Altera IP Evaluation Mode.

Nios® II Embedded Design Suite (EDS)—A full-featured set of tools that allows you to develop embedded software for the Nios® II processor, which you can include in your Altera FPGA designs.

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