Visible to Intel only — GUID: gdu1700458181337
Ixiasoft
Visible to Intel only — GUID: gdu1700458181337
Ixiasoft
6.3.2.5. JTAG Chain
This control shows all the devices currently in the JTAG chain. The Cyclone V GT device is always the first device in the chain. The JTAG chain is normally mastered by the On-board Intel® FPGA Download Cable II.
If you plug in an external download cable to the JTAG header (J13), the On-Board Intel® FPGA Download Cable II is disabled.
JTAG DIP switch bank (SW3) selects which interfaces are in the chain. Refer to Table 3 table for detailed settings.
For details on the JTAG chain, refer to the Cyclone® V GT FPGA Development Board Reference Manual. For Intel® FPGA Download Cable II configuration details, refer to the On-Board Intel® FPGA Download Cable II User Guide page.