AN 1005: Signal Tap Logic Analyzer Getting Started Tutorial

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ID 792742
Date 2/15/2024
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2.6. Step 6: Set Trigger Conditions

Follow these steps to set the trigger conditions for Signal Tap capture:

  1. In the Signal Tap Setup tab, select the count_binary[0] to count_binary[3] signals, right-click and then click Group. This action groups the signals into a bus.
    Figure 9. Grouping count_binary Bus


  2. Repeat step 1 to group the signals for seven_seg[0] to seven_seg[6].
    Figure 10. Grouping Results


  3. To view the data for count_binary[0..3] in binary format, right-click count_binary[0..3], and then click Bus Display Format > Binary.
    Figure 11. Selecting Binary Display Format


  4. To better represent and easily read signals for seven_seg[0..6], right-click seven_seg[0..6], then click Mnemonic Table Setup. The Mnemonic Table Setup dialog box appears.
    Figure 12. Mnemonic Table Setup


  5. Click the Add Table button, specify Seven Segment Display for the Name and a Width of 7. Click OK.
  6. Double-click <<new>> in the Pattern cell to add the mnemonic pattern.
    Figure 13. New Cell in Mnemonic Table Setup


  7. For example, to add number nine as a seven-segment mnemonic pattern, click Add Entry, and then specify the following values in the Add Entry dialog box before clicking OK:
    • Value—010000
    • Radix—Binary
    • Mnemonic—nine
    • Wrap search—Enable
    Figure 14. Mnemonic Table Setup
  8. Continue to fill the Pattern based on Value Representation for count_binary and seven_seg Registers, as Complete Pattern in Mnemonic Table Setup shows. Click OK when complete.
    Figure 15. Complete Pattern in Mnemonic Table Setup


  9. To set the display format for seven_seg[0..6], right-click seven_seg[0..6] in Trigger Conditions, and then click Bus Display Format > Seven Segment Display : width = 7.
  10. To set seven_seg[0..6] as the current trigger conditions, double-click the seven_seg[0..6] cell, and then type five in the Trigger Conditions column.
    Figure 16. Set Current Trigger Conditions


  11. To compile the design that includes this Signal Tap instance, click Processing > Start Compilation in the Intel Quartus Prime software. Close the Timing Analyzer that automatically appears following successful compilation.
  12. In the Signal Tap logic analyzer, program the board and click Run analysis. The following figure shows the expected result with seven_seg[0..6] == five as the trigger.
    Figure 17. Expected Results


  13. To expand the bus group and view the signal for each sample, click the + icon
    Figure 18. Expanded Group


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