AN 1005: Signal Tap Logic Analyzer Getting Started Tutorial

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ID 792742
Date 2/15/2024
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2.2. Step 2: Programming the FPGA for Signal Tap Use

Before programming the FPGA for use with Signal Tap, you must first create the connection between the Signal Tap logic analyzer and the Intel® Arria® 10 SX SoC Development Kit board via the Intel FPGA Download Cable II (USB-Blaster II), as the following steps describe:
  1. Connect the power supply to the Intel® Arria® 10 SX SoC Development Kit board.
  2. Connect the USB Blaster cable between your PC USB port and the USB Blaster port on the development board.
  3. In the Signal Tap Logic Analyzer window, under JTAG Chain Configuration, specify the following JTAG settings for this tutorial:
    • Hardware—USB-BlasterII
    • Device—10AS066H
    • SOF Manager—<project>/output_files/counter.sof
    Figure 3. JTAG Chain Configuration in Signal Tap


  4. To program the board for Signal Tap use, click the Program Device button.
  5. When programming is complete, Signal Tap displays the 'Ready to acquire' status under Instance Manager.
  6. To run the Signal Tap analysis, click the Run Analysis button.
    Figure 4. Run Analysis Button


  7. After analysis complete, the data acquisition appears in the Data tab.

    The trigger for the data acquisition was set to 9 for count_binary[0..3]. Data acquisition begins or is triggered when the value of count_binary[0..3] is 9, and seven_seg[0..6] vector starts displaying its corresponding value.

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