1.2. Signal Tap Tutorial Design Description
For every 49,999,999 of counter_50M, counter_10 increases by 1 from 0 to 9 and rolls over to 0.
The output register seven_seg corresponds to the value of counter_10 from 0 – 9 in the form of a common anode value for a seven segment display.
| Decimal Representation | Binary Representation [3:0] | Seven Segments [6:0] |
|---|---|---|
| 0 (zero) | 0000 | 1000000 |
| 1 (one) | 0001 | 1111001 |
| 2 (two) | 0010 | 0100100 |
| 3 (three) | 0011 | 0110000 |
| 4 (four) | 0100 | 1001001 |
| 5 (five) | 0101 | 0010010 |
| 6 (six) | 0110 | 0000010 |
| 7 (seven) | 0111 | 1111000 |
| 8 (eight) | 1000 | 0000000 |
| 9 (nine) | 1001 | 0010000 |
At the board level, the tutorial design connects the clock to a 50 MHz source, and connects the outputs to the seven_seg and count_binary registers. These outputs do not connect to any physical pins, but only to virtual pins. This example uses virtual pins because the Intel® Arria® 10 SX SoC Development Kit does not include a seven segment display.
A virtual pin is an I/O element that the Intel® Quartus® Prime Compiler temporarily maps to a logic element during compilation, rather than mapping to a pin. For more information on using virtual pins, refer to Defining Virtual Pins in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.
If you are using other boards or devices, you can change clk_50MHz to another general-purpose clock. To change the pin for clk_50MHz, click after opening the project.