Intel® Simics® Simulator for Intel® FPGAs: Agilex™ 5 E-Series Virtual Platform User Guide
ID
786901
Date
4/01/2024
Public
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1. About This Document
2. Agilex™ 5 E-Series Intel® Simics® Virtual Platforms
3. Agilex™ 5 E-Series Virtual Platform Component Intel® Simics® Models
4. Running a Simulation with the Agilex™ 5 E-Series HPS Model
5. Supported Use Cases
6. Troubleshooting Issues When Migrating Software from Intel® Simics® to Hardware
A. Document Revision History
2.1.3.1. Boot-To-Operating System Prompt
2.1.3.2. Basic Ethernet
2.1.3.3. CPU Power-On and Boot Core Selection
2.1.3.4. Reset Flow
2.1.3.5. General Purpose I/O (GPIO) Loopback
2.1.3.6. USB Disks Hot-Plug Support
2.1.3.7. On-Chip Memory IP FPGA Fabric Example Design
2.1.3.8. FPGA-to-HPS Bridges
2.1.3.9. Exercising Peripheral Subsystem in FPGA Fabric Design
2.1.3.10. USB Controller Host/Device Mode Configuration
2.1.3.11. B0 Silicon Features Selection
3.1.3. MPU and APS Subsystem
The following table lists the support status for components integrated into the MPU and APS subsystems. The table also indicates any component limitations and the object created under the HPS Intel® Simics® model of the Agilex™ 5 E-Series HPS.
Component | Supported? | Limitations | Objects |
---|---|---|
MPU Sub-System | Yes |
|
CoreSight Debug and Trace | No | N/A |
Interrupt Controller | Yes | Object: system.board.fpga.soc_inst.hps_subsys.agilex_hps.gic |
Cache Coherency Unit (CCU) | Yes |
|