AN 1002: Sharing Platform Designer Packaged Subsystems

ID 786899
Date 10/02/2023
Public
Document Table of Contents

5.2. Step 2: Add Components to the User System

After creating the packaged subscript user system, follow these steps to add Intel FPGA IP components from the IP Catalog to the system.

  1. From Platform Designer's IP Catalog, instantiate the following components into the system. Keep the defaults for all other parameters.
    Table 4.  User System Subsystem IP Parameters and Module Names
    Intel FPGA IP Parameters To Specify HDL Entity Name
    Reset Bridge Intel FPGA IP
    • Active low reset—Enable
    • Synchronous edgesdeassert
    cpu_reset_bridge
    Clock Bridge Intel FPGA IP Explicit clock rate100000000 Hz mgmt_clk
    On-Chip Memory Intel FPGA IP Total memory size285696 bytes onchip_mem
    JTAG UART Intel FPGA IP Write FIFO Buffer Depth—1024 jtag_uart
    Interval Timer Intel FPGA IP Units—us sys_clock_timer
    Avalon I2C Intel FPGA IP Depth of Fifo32 i2c_master
    System ID Peripheral Intel FPGA IP N/A sysid
    Nios V/m Microcontroller Intel FPGA IP1 Turn on Enable Reset from Debug Modules cpu
    Clock Bridge Intel FPGA IP Explicit clock rate16000000 Hz dp_rx_clk_16
    Reset Bridge Intel FPGA IP
    • Active low reset—Enable
    • Synchronous edgesNone
    dp_rx_reset_bridge
    Clock Bridge Intel FPGA IP Explicit clock rate16000000 Hz dp_tx_clk_16
    Reset Bridge Intel FPGA IP
    • Active low reset—Enable
    • Synchronous edgesNone
    dp_tx_reset_bridge
  2. Click File > Save to save the system. You can ignore any errors or warnings about the system at this point.
Figure 25. user_system Components in the System View Tab


1 This configuration is for demonstration purposes only, as actually BSP generation is not possible for designs with a Nios V/m or Nios II processor connected to a peripheral in a packaged subsystem.