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4.4.1. Editing the Packaged Subsystem
4.4.2. Step 4a: Add Two Checkbox Controls
4.4.3. Step 4b: Enable or Disable Modules and Checkboxes
4.4.4. Step 4c: Run run_system_script
4.4.5. Step 4d: Iterate Over All Parameters
4.4.6. Step 4e: Setting DisplayPort IP Functionality
4.4.7. Step 4f: Make Packaged Subsystem Unlockable
4.4.8. Step 4g: Sync System Infos, Assign Base Addresses, and Save
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5.2. Step 2: Add Components to the User System
After creating the packaged subscript user system, follow these steps to add Intel FPGA IP components from the IP Catalog to the system.
- From Platform Designer's IP Catalog, instantiate the following components into the system. Keep the defaults for all other parameters.
Table 4. User System Subsystem IP Parameters and Module Names Intel FPGA IP Parameters To Specify HDL Entity Name Reset Bridge Intel FPGA IP - Active low reset—Enable
- Synchronous edges—deassert
cpu_reset_bridge Clock Bridge Intel FPGA IP Explicit clock rate—100000000 Hz mgmt_clk On-Chip Memory Intel FPGA IP Total memory size—285696 bytes onchip_mem JTAG UART Intel FPGA IP Write FIFO Buffer Depth—1024 jtag_uart Interval Timer Intel FPGA IP Units—us sys_clock_timer Avalon I2C Intel FPGA IP Depth of Fifo—32 i2c_master System ID Peripheral Intel FPGA IP N/A sysid Nios V/m Microcontroller Intel FPGA IP1 Turn on Enable Reset from Debug Modules cpu Clock Bridge Intel FPGA IP Explicit clock rate—16000000 Hz dp_rx_clk_16 Reset Bridge Intel FPGA IP - Active low reset—Enable
- Synchronous edges—None
dp_rx_reset_bridge Clock Bridge Intel FPGA IP Explicit clock rate—16000000 Hz dp_tx_clk_16 Reset Bridge Intel FPGA IP - Active low reset—Enable
- Synchronous edges—None
dp_tx_reset_bridge - Click File > Save to save the system. You can ignore any errors or warnings about the system at this point.
Figure 25. user_system Components in the System View Tab
1 This configuration is for demonstration purposes only, as actually BSP generation is not possible for designs with a Nios V/m or Nios II processor connected to a peripheral in a packaged subsystem.