Intel Agilex® 7 Device Family Pin Connection Guidelines: M-Series

ID 776197
Date 9/27/2023
Document Table of Contents

1.2.8. Reference Pins

Note: Intel recommends that you create an Intel® Quartus® Prime design, enter your device I/O assignments, and compile the design. The Intel® Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device handbook.
Table 8.  Reference Pins
Pin Name Pin Functions Pin Description Connection Guidelines




Reference pins for I/O banks. The RZQ pins share the same VCCIO_PIO with the I/O bank where they are located.

Connect the external precision resistor to the designated pin within the bank. If not required, this pin is a regular I/O pin.

These pins support 1.3-V, 1.2-V, 1.1-V, and 1.05-V I/O standards.

These pins support the programmable pull-up resistor. For more information, refer to the Intel Agilex® 7 M-Series Device Data Sheet.

For more information about the supported pins, refer to the device pin-out file.

When using OCT, tie these pins to GND through a 240-Ω resistor.

When you do not use these pins as dedicated input for the external precision resistor or as I/O pins, leave these pins unconnected.