Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

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ID 776197
Date 8/11/2025
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Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series x
1.1. Pin Connection Guideline Status for Agilex™ 7 M-Series Devices 1.2. Agilex™ 7 M-Series FPGA Core Pins 1.3. Agilex™ 7 M-Series HBM2E Pins 1.4. Agilex™ 7 M-Series F-Tile Pins 1.5. Agilex™ 7 M-Series R-Tile Pins 1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins 1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines 1.8. Notes to Agilex™ 7 M-Series Device Family Pin Connection Guidelines 1.9. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: M-Series
1.2. Agilex™ 7 M-Series FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 M-Series HBM2E Pins x
1.3.1. HBM2E Power Supply Pins 1.3.2. HBM2E Signal Pins
1.4. Agilex™ 7 M-Series F-Tile Pins x
1.4.1. F-Tile Power Supply Pins 1.4.2. F-Tile Transceiver Pins
1.5. Agilex™ 7 M-Series R-Tile Pins x
1.5.1. R-Tile Power Supply Pins 1.5.2. R-Tile Transceiver Pins
1.6. Agilex™ 7 M-Series Hard Processor System (HPS) Pins x
1.6.1. HPS Supply Pins 1.6.2. HPS Oscillator Clock Input Pin 1.6.3. HPS JTAG Pins 1.6.4. HPS GPIO Pins 1.6.5. HPS SDMMC Pins 1.6.6. HPS NAND Pins 1.6.7. HPS USB Pins 1.6.8. HPS EMAC Pins 1.6.9. HPS I2C_EMAC and MDIO Pins 1.6.10. HPS I2C Pins 1.6.11. HPS SPI Pins 1.6.12. HPS UART Pins 1.6.13. HPS Trace Pins
1.7. Agilex™ 7 M-Series Power Supply Sharing Guidelines x
1.7.1. Example 1— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR4 1.7.2. Example 2— Agilex™ 7 M-Series Devices with R-Tile, F-Tile and HBM2E Using DDR5 1.7.3. Example 3— Agilex™ 7 M-Series Devices with R-Tile and F-Tile, Without HBM2E Using DDR4 1.7.4. Example 4— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR4 1.7.5. Example 5— Agilex™ 7 M-Series Devices with F-Tile only and HBM2E Using DDR5 1.7.6. Example 6— Agilex™ 7 M-Series Devices with F-Tile only and Without HBM2E Using DDR5
1. Agilex™ 7 Device Family Pin Connection Guidelines: M-Series

1.2.1. Clock and PLL Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Pin Name Pin Functions Pin Description Connection Guidelines

CLK_[T,B]_2[A,B,C,D,E,F]_[0:1][p,n]

CLK_[T,B]_3[A,B,C,D,E,F]_[0:1][p,n]

 I/O, Clock Input

Dual-purpose I/O pins that can be used for data inputs or outputs. On-chip termination such as differential input termination (RD OCT), parallel termination (RT OCT), and series termination (RS OCT) are supported on these pins.

For more information about the supported pins, refer to the device pin-out file.

When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins.

Supported I/O standards:

  • 1.05 V
  • 1.1 V
  • 1.2 V
  • 1.3 V

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series .

 If the entire GPIO-B bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active GPIO-B bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.

PLL_[2] [A,B,C,D,E,F]_[T,B]_FB[0:1]

PLL_[3] [A,B,C,D,E,F]_[T,B]_FB[0:1]

 I/O, Clock Input

Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins.

For more information about the supported pins, refer to the device pin-out file.

Supported I/O standards:

  • 1.05 V
  • 1.1 V
  • 1.2 V
  • 1.3 V

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series .

 If the entire GPIO-B bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active GPIO-B bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.

PLL_[2] [A,B,C,D,E,F]_[T,B]_CLKO UT[0:1][p,n]

PLL_[3] [A,B,C,D,E,F]_[T,B]_CLKO UT[0:1][p,n]

 I/O, Clock Output

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

For more information about the supported pins, refer to the device pin-out file.

Supported I/O standards:

  • 1.05 V
  • 1.1 V
  • 1.2 V
  • 1.3 V

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series .

 If the entire GPIO-B bank is unused, you may leave these pins floating, connected to VCCIO_PIO, or connected to a tri-stated upstream or downstream I/O pin. If the unused pins reside in an active GPIO-B bank, you may leave these pins floating or connected to a tri-stated upstream or downstream I/O pin.
REFCLK_NOC[00,01] Clock Input Reference clock input for network on a chip (NoC) phase-locked loop (PLL).

Connect 1.8-V single-ended 10 MHz–325 MHz clock to these pins. For better PLL performance, Altera recommends using 100 MHz–200 MHz clock for these reference clocks.

Tie it to GND or leave it floating if NoC is unused.
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