2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel®...

High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

Download PDF

ID 773266

Date 10/02/2023

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

Document Table of Contents x

1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide

1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide x

1.1. Release Information

2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide x

2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example 2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP

2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP x

2.5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation 2.5.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS* 2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE 2.5.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator 2.5.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project

3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description x

3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing

3.2. Use Cases x

3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support

1. About the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example User Guide

1.1. Release Information

2. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Design Example Quick Start Guide

2.1. Creating an Intel® Quartus® Prime Project for Your HBM2E System

2.2. Configuring the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP

2.3. Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation

2.4. Compiling and Programming the Intel Agilex® 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example

2.5. Simulating the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP

2.5.1. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Example Design For Simulation

2.5.2. Simulating High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP with Synopsys VCS*

2.5.3. Simulating the HBM2E Intel FPGA IP with ModelSim SE

2.5.4. Simulating the HBM2E Intel FPGA IP with Cadence* Xcelium Parallel Simulator

2.5.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project

3. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example Description

3.1. Design Example Components

3.2. Use Cases

3.2.1. Initiator to Target NoC Mapping

3.2.2. Fabric NoC

3.2.3. AXI4-Lite Support

3.3. Top-Level Signals of the HBM2E Design Example

3.4. Using the HBM2E Design Example for Performance Testing

4. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example User Guide