External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 3/31/2025
Public

Visible to Intel only — GUID: abi1658515077653

Ixiasoft

Document Table of Contents

11.9. Hardware Debugging Guidelines

Before debugging your design, confirm that it follows the recommended design flow. Refer to the Intel Agilex® 7 M-Series EMIF IP Design Flow section in chapter 1 of this user guide.

Always keep a record of tests, to avoid repeating the same tests later. To start debugging the design, perform the following initial steps.