External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 4/01/2024
Public
Document Table of Contents

8.2.4.2. LPDDR5 Data Width Mapping

The EMIF IP for Agilex™ 7 M-Series does not support flexible data lane placement.

Only fixed byte lanes within the I/O bank can be used as data lanes. The following table lists the supported address and command and data lane placements in an I/O bank.

Table 171.  Component
Controller Data Width Usage BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]   BL7 [P95:P84] BL6 [P83:P72] BL5 [P71:P60] BL4 [P59:P48] BL3 [P47:P36] BL2 [P35:P24] BL1 [P23:P12] BL0 [P11:P0]
Primary LPDDR5 x16 GPIO GPIO GPIO GPIO AC1 P AC0 P DQ[1] P DQ[0] P                  
Primary LPDDR5 x16 DQ[1] S DQ[0] S AC1 S AC0 S GPIO GPIO GPIO GPIO                  
Primary & Secondary LPDDR5 2ch x16 DQ[1] S DQS[0] S AC1 S AC0 S AC1 P AC0 P DQ[1] P DQ[0] P                  
Primary LPDDR5 x32 DQ[3] P DQ[2] P GPIO GPIO AC1 P AC0 P DQ[1] P DQ[0] P                  
Primary & Secondary LP DDR5 4ch x16 DQ[1] S DQ[0] S AC1 S AC0 S AC1 P AC0 P DQ[1] P DQ[0] P   DQ[1] S DQ[0] S AC1 S AC0 S AC1 P AC0 P DQ[1] P DQ[0] P
Note:
  • P Primary controller.
  • S Secondary controller.