External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 4/01/2024
Public
Document Table of Contents

3.3.1. Hard Memory Controller

The Agilex™ 7 M-Series hard memory controller is designed for high speed, high performance, high flexibility, and area efficiency. The Agilex™ 7M-Series hard memory controller supports the DDR4, DDR5, and LPDDR5 memory standards.

The hard memory controller implements efficient pipelining techniques and advanced dynamic command and data reordering algorithms to improve bandwidth usage and reduce latency, providing a high-performance solution.

The hard memory controller consists of the following logic blocks:

  • Core and PHY interfaces
  • Main control path
  • Data buffer controller
  • Read and write data buffers

The controller user interface uses the AXI4 protocol. The controller communicates to the PHY using the DDR PHY Interface (DFI).