External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

ID 772538
Date 12/04/2023
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6.2.2.1. OCT

You require an OCT calibration block if you are using an Intel Agilex® 7 M-Series FPGA OCT calibrated series, parallel, or dynamic termination for any I/O in your design. There are two OCT blocks in an I/O bank, one for each sub-bank.
  • You must observe the following requirements when using OCT blocks:

    The I/O bank where you place the OCT calibration block must use the same VCCIO_PIO voltage as the memory interface.
  • The OCT calibration block uses a single fixed RZQ . You must ensure that an external termination resistor is connected to the correct pin for a given OCT block.