External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

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ID 772538
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction 3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture 4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals 5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support 7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support 8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure 10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization 11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging 12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction x
2.1. Intel Agilex® 7 M-Series EMIF IP Protocol and Feature Support 2.2. Intel Agilex® 7 M-Series EMIF IP Design Flow 2.3. Intel Agilex® 7 M-Series EMIF IP Design Checklist
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction 3.2. Intel Agilex® 7 M-Series EMIF Sequencer 3.3. Intel Agilex® 7 M-Series EMIF Controller 3.4. Intel Agilex® 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Intel Agilex® 7 M-Series EMIF Architecture: Introduction x
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.2. Intel Agilex® 7 M-Series EMIF Sequencer x
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions
3.2.1. Intel Agilex® 7 M-Series Mailbox Structure and Register Definitions x
3.2.1.1. Mailbox Supported Commands 3.2.1.2. Mailbox Command Definitions
3.3. Intel Agilex® 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR4 4.2. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR5 4.3. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for LPDDR5 4.4. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for EMIF Calibration Component
4.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR4 x
4.1.1. ref_clk for EMIF 4.1.2. core_init_n for EMIF 4.1.3. usr_async_clk for EMIF 4.1.4. usr_clk for EMIF 4.1.5. usr_rst_n for EMIF 4.1.6. s0_axi4 for EMIF 4.1.7. mem for EMIF 4.1.8. oct for EMIF
4.2. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for DDR5 x
4.2.1. ref_clk for EMIF 4.2.2. core_init_n for EMIF 4.2.3. usr_async_clk for EMIF 4.2.4. usr_clk for EMIF 4.2.5. usr_rst_n for EMIF 4.2.6. s0_axi4 for EMIF 4.2.7. mem for EMIF 4.2.8. i3c for EMIF 4.2.9. mem_lbd for EMIF 4.2.10. mem_lbs for EMIF 4.2.11. oct for EMIF
4.3. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for LPDDR5 x
4.3.1. ref_clk for EMIF 4.3.2. core_init_n for EMIF 4.3.3. usr_async_clk for EMIF 4.3.4. usr_clk for EMIF 4.3.5. usr_rst_n for EMIF 4.3.6. s0_axi4 for EMIF 4.3.7. mem for EMIF 4.3.8. oct for EMIF
4.4. Intel Agilex® 7 M-Series FPGA EMIF IP Interfaces for EMIF Calibration Component x
4.4.1. s0_axi4lite_clk for EMIF 4.4.2. s0_axi4lite_rst_n for EMIF 4.4.3. s0_axi4lite for EMIF
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.3. DDR4 Board Design Guidelines
6.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR4 x
6.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for DDR4 6.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR4) Parameter Descriptions 6.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
6.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 6.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP
6.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
6.2.1.1. Estimating Pin Requirements 6.2.1.2. DIMM Options 6.2.1.3. Maximum Number of Interfaces
6.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
6.2.2.1. OCT 6.2.2.2. PLL
6.2.4. Pin Placements for Intel Agilex® 7 M-Series FPGA DDR4 EMIF IP x
6.2.4.1. Address and Command Pin Placement for DDR4 6.2.4.2. DDR4 Data Width Mapping 6.2.4.3. General Guidelines - DDR4 6.2.4.4. x4 DIMM Implementation 6.2.4.5. Specific Pin Connection Requirements 6.2.4.6. Command and Address Signals 6.2.4.7. Clock Signals 6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3. DDR4 Board Design Guidelines x
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices 6.3.2. General Layout Routing Guidelines 6.3.3. Reference Stackup 6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.3.1. Terminations for DDR4 with Intel Agilex® 7 M-Series Devices x
6.3.1.1. Dynamic On-Chip Termination (OCT) 6.3.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.3.1.3. Choosing Terminations on Intel Agilex® 7 M-Series FPGA Devices 6.3.1.4. On-Chip Termination Recommendations for Intel Agilex® 7 M-Series FPGA Devices
6.3.4. Intel Agilex® 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.3.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.3.4.2. Skew Matching Guidelines for DIMM Configurations 6.3.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.3.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.3.5.1. Single Rank x 8 Discrete (Component) Topology 6.3.5.2. Single Rank x 16 Discrete (Component) Topology 6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
6.3.5.6.1. DDR4 Byte Lane Swapping 6.3.5.6.2. DDR4 Address and Command and CLK Lane 6.3.5.6.3. DDR4 Interface x8 Data Lane 6.3.5.6.4. DDR4 Interface x4 Data Lane 6.3.5.6.5. Pin Swizzling
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.3. DDR5 Board Design Guidelines
7.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for DDR5 x
7.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for DDR5 7.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions 7.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
7.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP 7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
7.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
7.2.1.1. Estimating Pin Requirements 7.2.1.2. DIMM Options 7.2.1.3. Maximum Number of Interfaces
7.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
7.2.2.1. OCT 7.2.2.2. PLL
7.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
7.2.3.1. General Guidelines - DDR5 7.2.3.2. x4 DIMM Implementation 7.2.3.3. Specific Pin Connection Requirements 7.2.3.4. Command and Address Signals 7.2.3.5. Clock Signals 7.2.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA DDR5 EMIF IP x
7.2.4.1. Address and Command Pin Placement for DDR5 7.2.4.2. DDR5 Data Width Mapping
7.2.5. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines x
7.2.5.1. DDR5 Byte Lane Swapping 7.2.5.2. DDR5 Address and Command and CLK Lane 7.2.5.3. DDR5 Interface x8 Data Lane 7.2.5.4. DDR5 Interface x4 Data Lane 7.2.5.5. Pin Swizzling
7.3. DDR5 Board Design Guidelines x
7.3.1. PCB Stack-up and Design Considerations 7.3.2. General Design Considerations 7.3.3. DDR Differential Signals Routing 7.3.4. Ground Plane and Return Path 7.3.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.3.6. DRAM Break-in Layout Guidelines 7.3.7. DDR5 PCB Layout Guidelines 7.3.8. DDR5 Simulation Strategy
7.3.7. DDR5 PCB Layout Guidelines x
7.3.7.1. DDR5 Discrete Component/Memory Down Topology: up to 40-Bit Interface (1 Rank x8 or x16, 2 Rank x8 or x16) 7.3.7.2. Routing Guidelines for DDR5 Memory Down: 1 Rank or 2 Rank (x8 bit or x16 bit) Configurations 7.3.7.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.3.7.4. Example of a DDR5 layout on Intel FPGA Platform Board
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.1. Intel Agilex 7 M-Series FPGA EMIF IP Parameters for LPDDR5 x
8.1.1. Intel Agilex® 7 FPGA EMIF IP Parameter for LPDDR5 8.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (LPDDR5) Parameter Descriptions 8.1.3. Intel Agilex 7 FPGA EMIF Calibration IP Parameter Descriptions
8.2. Intel Agilex® 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Intel Agilex® 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. DIMM Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Intel Agilex® 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Intel Agilex® 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Intel Agilex 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. LPDDR5 PCB Layout Guidelines 8.3.7. LPDDR5 Simulation Strategy
8.3.6. LPDDR5 PCB Layout Guidelines x
8.3.6.1. LPDDR5 Discrete Component/Memory Down Topology (1 Rank or 2 Rank, up to 64 Bit Interface) 8.3.6.2. Supported LPDDR5 Topologies 8.3.6.3. Example of an LPDDR5 Layout on an Intel® FPGA Platform Board
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Generating Traffic with the Test Engine IP 11.6. Guidelines for Developing HDL for Traffic Generator 11.7. Debugging with the External Memory Interface Debug Toolkit
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Intel® IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.7. Debugging with the External Memory Interface Debug Toolkit x
11.7.1. Prerequisites for Using the EMIF Debug Toolkit 11.7.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.7.3. Launching the EMIF Debug Toolkit 11.7.4. Using the EMIF Debug Toolkit
11.7.4. Using the EMIF Debug Toolkit x
11.7.4.1. Rerunning Calibration 11.7.4.2. Rerunning the Test Engine 11.7.4.3. Saving Debug Print 11.7.4.4. Calibration Reports 11.7.4.5. Driver Margining Tab 11.7.4.6. Pin Delay Settings Tab
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide

7.1.2. Intel Agilex 7 FPGA EMIF Memory Device Description IP (DDR5) Parameter Descriptions

The following topics describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP. Each parameter with an adjacent checkbox can be auto-computed. The checkbox to the left of the parameter controls whether its value is auto-computed (true) or set manually (false). If there is no checkbox to the left of a parameter, then it must be set manually.
Table 116.  Group: Configuration Save
Display Name Description
Configuration Filepath

Filepath to Save to (.qprs extension)

(Identifier: MEM_CONFIG_FILE_QPRS)
Table 117.  Group: High-Level Parameters
Display Name Description
Memory Format

Specifies the packaging format of the memory device

(Identifier: MEM_FORMAT)
Enable Data Mask

Specifies whether byte masking is to be enabled by the memory.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_DM_EN)
Density of Each Memory Component

Specifies the density of each memory component in Gbits.

(Identifier: DDR5_MEM_DEVICE_DENSITY_GBITS)
Table 118.  Group: Memory Interface Parameters / Data Bus
Display Name Description
Device DQ Width

If the device is a DIMM: Specifies the full DQ width of the DIMM.

If the interface is composed of discrete components: Specifies the DQ width of each discrete component.

(Identifier: MEM_DEVICE_DQ_WIDTH)
Memory Component Data Width

Specifies the data width of the memory component in bits.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_COMPONENT_DQ_WIDTH)
Burst Length

Specifies the burst length of the memory interface.

(Identifier: DDR5_MEM_DEVICE_BURST_LENGTH)
Table 119.  Group: Memory Interface Parameters / Device Topology
Display Name Description
Number of Ranks per DIMM

Number of ranks per DIMM

Note: This parameter can be auto-computed.

(Identifier: MEM_RANKS_PER_DIMM)
Number of Channels Per DIMM

Number of channels per DIMM

Note: This parameter can be auto-computed.

(Identifier: MEM_CHANNELS_PER_DIMM)
Device Bank Group Address Width

Specifies the width of the bank group address.

(Identifier: DDR5_MEM_DEVICE_BANK_GROUP_ADDR_WIDTH)
Device Bank Address Width

Specifies the width of the bank address.

(Identifier: DDR5_MEM_DEVICE_BANK_ADDR_WIDTH)
Device Row Address Width

Specifies the width of the row address.

(Identifier: DDR5_MEM_DEVICE_ROW_ADDR_WIDTH)
Device Column Address Width

Specifies the width of the column address.

(Identifier: DDR5_MEM_DEVICE_COL_ADDR_WIDTH)
Number of Differential Memory Clock Pairs

Specifies the width of clock interface according to the number of ranks.

(Identifier: DDR5_MEM_DEVICE_CK_WIDTH)
Table 120.  Group: Memory Timing Parameters / Timing Parameters
Display Name Description
Memory Clock Frequency

Specifies the operating frequency of the memory interface in MHz. If you change the memory frequency, you must select a matching Preset from the dropdown (or create a custom one), to update all the timing parameters.

Note: This parameter can be auto-computed.

(Identifier: PHY_MEMCLK_FREQ_MHZ)
Memory Speed Bin

Specifies the memory speed bin.

(Identifier: DDR5_MEM_DEVICE_SPEEDBIN)
Memory Read Latency

Specifies the read latency of the memory interface in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_CL_CYC)
Memory Write Latency

Specifies the write latency of the memory interface in cycles.

(Identifier: DDR5_MEM_DEVICE_CWL_CYC)
Table 121.  Group: Memory Timing Parameters / Advanced Timing Parameters
Display Name Description
tREFI1

Specifies the maximum average refresh interval in normal refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TREFI1_NS)
tREFI2

Specifies the maximum average refresh interval in fine granularity refresh mode in nanoseconds.

(Identifier: DDR5_MEM_DEVICE_TREFI2_NS)
tREFISB

Specifies the maximum average refresh interval in fine granularity and same bank refresh mode in nanoseconds.

(Identifier: DDR5_MEM_DEVICE_TREFISB_NS)
tCCD_S

Specifies the CAS_n to CAS_n command delay for different bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_S_CYC)
tCCD_L

Specifies the CAS_n to CAS_n command delay for same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_L_CYC)
tCCD_L_WR

Specifies the write CAS_n to write CAS_n command delay for same bank group in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_L_WR_CYC)
tCCD_L_WR2

Specifies the write CAS_n to write CAS_n command delay for same bank group and the second write is not RMW, in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCCD_L_WR2_CYC)
tRRD_S

Specifies the Activate-to-Activate command delay to different bank group for 1KB page size in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRRD_S_CYC)
tRRD_L

Specifies the Activate-to-Activate command delay to same bank group for 1KB page size in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRRD_L_CYC)
tFAW

Specifies the four activate window for 1KB page size in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TFAW_NS)
tRFC1

Specifies the refresh operation delay in normal refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRFC1_NS)
tRFC2

Specifies the refresh operation delay in fine granularity refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRFC2_NS)
tRFCSB

Specifies the refresh operation delay in fine granularity and same bank refresh mode in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRFCSB_NS)
tRCD

Specifies the Activate-to-internal-Read-or-Write delay in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRCD_NS)
tRP

Specifies the row precharge time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRP_NS)
tRAS

Specifies the Activate-to-Precharge command period in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRAS_NS)
tRC (tRAS+tRP)

Specifies the Activate-to-Activate or Refresh command period in nanoseconds.

(Identifier: DDR5_MEM_DEVICE_TRC_NS)
tREFSBRD

Specifies the same bank refresh to activate delay in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TREFSBRD_NS)
tWR

Specifies the write recovery time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWR_NS)
tZQLAT

Specifies the ZQ calibration latch time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TZQLAT_CYC)
tZQCAL

Specifies the ZQ calibration time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TZQCAL_NS)
tMRR

Specifies the Mode Register Read (MRR) command period in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRR_CYC)
tMRR_P

Specifies the Mode Register Read (MRR) pattern to mode register read pattern command spacing in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRR_P_CYC)
tMRW

Specifies the Mode Register Write (MRW) command period in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRW_CYC)
tMRD

Specifies the Mode Register Set (MRS) command delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TMRD_CYC)
tDFE

Specifies the Decision Feedback Equalization (DFE) Mode Register Write update delay time in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDFE_NS)
tDLLK

Specifies the timing of DLLK in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDLLK_CYC)
tWTR_S

Specifies the delay from start of internal write transaction to internal read command for different bank group in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWTR_S_NS)
tWTR_L

Specifies the delay from start of internal write transaction to internal read command for same bank group in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWTR_L_NS)
tRTP

Specifies the internal read command to precharge command delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TRTP_CYC)
tPPD

Specifies the Precharge-to-Precharge delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TPPD_CYC)
tPD

Specifies the minimum power down time in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TPD_CYC)
tACTPDEN

Specifies the timing of Activate command to power down entry command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TACTPDEN_CYC)
tPRPDEN

Specifies the timing of Precharge All Banks (PREab), Precharge Same Bank (PREsb), or Normal Precharge (PREpb) to power down entry command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TPRPDEN_CYC)
tREFPDEN

Specifies the timing of Refresh All Banks (REFab) or Refresh Same Bank (REFsb) command to power down entry command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TREFPDEN_CYC)
tXP

Specifies the exit power down to next valid command in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TXP_CYC)
tCPDED

Specifies the command pass disable delay in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCPDED_CYC)
tCSL

Specifies the Self-Refresh CS_n low pulse width in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCSL_NS)
tCKSRX

Specifies the valid clock requirement before SRX in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCKSRX_CYC)
tCSH_SREXIT

Specifies the self-refresh exit CS_n high pulse width in nanoseconds.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TCSH_SREXIT_NS)
tDQSCK

Specifies the DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDQSCK_CYC)
tWPRE_EN

Specifies the write preamble enable window in cycles. The window size depends on the write preamble mode.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TWPRE_EN_CYC)
tDQSS

Specifies the host and system voltage/temperature drift window of first rising DQS_t preamble edge relative to CAS Write Latency (CWL) CK_t-CK_c edge in cycles.

Note: This parameter can be auto-computed.

(Identifier: DDR5_MEM_DEVICE_TDQSS_CYC)
Level Two Title