Intel® FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 7/03/2023

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4.2. Build Options

The runtime folder in the design example package contains a script to build the runtime called
Issue the following command to run the script:
./ <command_line_options>
Where <command_line_options> are defined in the following table:
Table 2.  Command Line Options for the Script
Command Description
-h | --help Show usage details
--cmake_debug Call cmake with a debug flag
--verbosity=<number> Large numbers add some extra verbosity
--build_dir=<path> Directory where the runtime build should be placed

If this flag is specified, then the runtime will only support the Ahead of Time mode. The runtime will not link to the precompiled compiler libraries.

Use this mode when trying to compile the runtime on an unsupported operating system.
--build_demo Adds several OpenVINO™ demo applications to the runtime build. The demo applications are in subdirectories of the runtime/directory.
--de10_agilex Target the Terasic* DE10-Agilex Development Board.

If this option is not specified, then the runtime will by default target the Intel® PAC with Intel® Arria® 10 GX FPGA.

--aot_splitter_example Builds the AOT splitter example utility for the selected target ( Intel® PAC with Intel® Arria® 10 GX FPGA or Terasic* DE10-Agilex Development Board).

This option builds an AOT file for a model, splits the AOT file into its constituent components (weights, overlay instructions, etc), and the builds a small utility that loads the model and a single image onto the target FPGA board without using OpenVINO™ .

You must set the $AOT_SPLITTER_EXAMPLE_MODEL and $AOT_SPLITTER_EXAMPLE_INPUT environment variables correctly. For details, refer to " Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application" in Intel® FPGA AI Suite IP Reference Manual .

The Intel FPGA AI Suite runtime plugin is built in release mode by default. To enable debug mode, you must specify the -cmake_debug option of the script command.

The -no_make option skips the final call to the make command. You can make this call manually instead.

Intel FPGA AI Suite hardware is compiled to include one or more IP instances, with the same architecture for all instances. Each instance accesses data from a unique bank of DDR:

  • An Intel Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA has two DDR banks and supports two instances.
  • The Terasic DE10-Agilex board supports up to four instances.

The runtime automatically adapts to the correct number of instances.

If the Intel FPGA AI Suite Runtime uses two or more instances, then the image batches are divided between the instances to execute two or more batches in parallel on the FPGA device.