Intel® FPGA AI Suite: PCIe-based Design Example User Guide

ID 768977
Date 9/06/2023

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Document Table of Contents

6.1.2. Script Flow

The following steps describe the internal flow of the script for the Arria 10 PAC:
  1. Runs the dla_create_ip script to create an Intel FPGA AI Suite IP for the requested IntelFPGA AI Suite architecture
  2. Creates a wrapper around the IntelFPGA AI Suite IP instances and adapter logic
  3. Runs the OPAE afu_synth_setup script to create a build directory that has the BSP infrastructure needed to compile the design with Intel® Quartus® Prime software.
  4. Runs the OPAE script to compile the design example with Intel® Quartus® Prime software:
    1. Compile the example design up to and including bitstream generation.
    2. Analyze the timing report to extract the Intel FPGA AI Suite clock maximum frequency (fMAX).
    3. Create an AFU/AF bitstream (green bitstream) file with PLL configurations to generate a clock that is slightly lower than the fMAX of the design.
  5. Runs the OPAE PACSign script to generate an unsigned version of the AFU/AF bitstream as well as a signed version.

The script uses the Intel® Quartus® Prime timing analyzer to report the top critical paths of the compiled design example.

The unsigned and signed versions of the bitstreams are in the <build_dir> directory that you set when running the script (or the default location, if you did not set it). The signed and unsigned bitstream file names are dla_afu.gbs and dla_afu_unsigned.gbs, respectively.

The Intel® Quartus® Prime compilation reports are available in the <build_dir>/build/output_files directory. A build.log file that has all the output log for running the build script is available in the <build_dir> directory. In addition, the achieved Intel FPGA AI Suite clock frequency is the clock-frequency-low value in the following file: