Intel® FPGA AI Suite: PCIe-based Design Example User Guide

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ID 768977
Date 9/06/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide 2. About the PCIe* -based Design Example 3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example 4. Building the Intel® FPGA AI Suite Runtime 5. Running the Design Example Demonstration Applications 6. Design Example Components 7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History
4. Building the Intel® FPGA AI Suite Runtime x
4.1. CMake Targets 4.2. Build Options
5. Running the Design Example Demonstration Applications x
5.1. Exporting Trained Graphs from Source Frameworks 5.2. Compiling Exported Graphs Through the Intel FPGA AI Suite 5.3. Compiling the PCIe* -based Example Design 5.4. Programming the FPGA Device ( Intel® Arria® 10) 5.5. Programming the FPGA Device ( Intel Agilex® 7) 5.6. Performing Accelerated Inference with the dla_benchmark Application 5.7. Running the Ported OpenVINO™ Demonstration Applications
5.6. Performing Accelerated Inference with the dla_benchmark Application x
5.6.1. Inference on Image Classification Graphs 5.6.2. Inference on Object Detection Graphs 5.6.3. Additional dla_benchmark Options
5.6.2. Inference on Object Detection Graphs x
5.6.2.1. The mAP and COCO AP Metrics 5.6.2.2. Specifying Ground Truth 5.6.2.3. Example of Inference on Object Detection Graphs
5.7. Running the Ported OpenVINO™ Demonstration Applications x
5.7.1. Example Running the Object Detection Demonstration Application
6. Design Example Components x
6.1. Build Script 6.2. Example Architecture Bitstream Files 6.3. Software Components 6.4. Software Interface to the BSP
6.1. Build Script x
6.1.1. Build Script Options 6.1.2. Script Flow
6.3. Software Components x
6.3.1. OpenVINO™ FPGA Runtime Plugin 6.3.2. Intel FPGA AI Suite Runtime 6.3.3. BSP Driver
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA x
7.1. System Overview 7.2. Hardware
7.2. Hardware x
7.2.1. PLL Adjustment
1. Intel® FPGA AI Suite PCIe-based Design Example User Guide
2. About the PCIe* -based Design Example
3. Getting Started with the Intel® FPGA AI Suite PCIe* -based Design Example
4. Building the Intel® FPGA AI Suite Runtime
5. Running the Design Example Demonstration Applications
6. Design Example Components
7. Design Example System Architecture for the Intel PAC with Intel® Arria® 10 GX FPGA
A. Intel® FPGA AI Suite PCIe-based Design Example User Guide Archives
B. Intel® FPGA AI Suite PCIe-based Design Example User Guide Document Revision History

6.1.1. Build Script Options

Table 5.  Build Script Options
Option Description
-a, --archs Path to Intel FPGA AI Suite IP Architecture Description File
-d, --archs-dir Path to directory that contains Architecture Description Files for you to interactively choose from (alternative to ‘-a’)
-ed, --example-design-id

To build for the Intel PAC with Intel® Arria® 10 GX FPGA board, specify 1.

To build for the Terasic DE10-Agilex board, specify 3.

(default: 1)
-n, --num-instances

Number of IP instances to build (default: 2).

For the Intel PAC with Intel® Arria® 10 GX FPGA board, this number must be either 1 or 2.

For the Terasic DE10-Agilex board, this number must be 1, 2, 3, or 4.

--build Option to perform compilation of the PCIe* design using Intel® Quartus® Prime after instantiation (default: False).
--build-dir

Path to hardware build directory where BSP infrastructure and generated RTL will be located.

(default: coredla/pcie_ed/platform/build_synth)

-s, --seed Seed to be used in compiling the design (default: 1).
--num-paths Number of top critical paths to report after compiling the design (default: 2000).
--qor-modules List of internal modules (instance names) from inside the IP to include in the QoR summary report.
-q, --quiet Run script quietly without printing the output of underlying scripts to the terminal.
--unlicensed/licensed
This option is passed to the dla_create_ip tool to tell the tool to generate either an unlicensed or licensed copy of the Intel® FPGA AI Suite:
  • Unlicensed IP: Unlicensed IP has a limit of 10000 inferences. After 10000 inferences, the unlicensed IP refuses to perform any additional inference and a bit in the CSR is set. For details about the CSR bit, refer to DMA Descriptor Queue in Intel® FPGA AI Suite IP Reference Manual .
  • Licensed IP: Licensed IP has no inference limitation.

If you do not have a license but generate licensed IP, Quartus cannot generate a bitstream.

If neither option is specified, then the dla_create_ip tool queries the lmutil license manager to determine the correct option.

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