Intel® FPGA AI Suite: IP Reference Manual

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ID 768974
Date 12/01/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite IP Reference Manual 2. About the Intel® FPGA AI Suite IP 3. Intel® FPGA AI Suite IP Generation Utility 4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. Intel® FPGA AI Suite IP Reference Manual Archives B. Intel® FPGA AI Suite IP Reference Manual Document Revision History
2. About the Intel® FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Intel® FPGA AI Suite Layer / Primitive Ranges 2.4. Intel® FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. Intel® FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter Group: Global Parameters 2.4.2.2. Parameter Group: activation 2.4.2.3. Parameter Group: pe_array 2.4.2.4. Parameter Group: pool 2.4.2.5. Module: softmax 2.4.2.6. Parameter Group: dma 2.4.2.7. Parameter Group: xbar 2.4.2.8. Parameter Group: filter_scratchpad 2.4.2.9. Parameter Group: config_network
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping
3. Intel® FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers 5.6. Debug Network Registers
1. Intel® FPGA AI Suite IP Reference Manual
2. About the Intel® FPGA AI Suite IP
3. Intel® FPGA AI Suite IP Generation Utility
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. Intel® FPGA AI Suite IP Reference Manual Archives
B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

2.5.4.4. Input Transform Mapping

To help make sense of how input data is transformed for a compiled graph, the Intel® FPGA AI Suite compiler creates the following CSV files:
  • input_transform_dump_<graph-name>.csv

    This file describes the tensor shape, padding, and stride for each input tensor.

  • input_transform_mapping_<graph-name>.csv

    This file shows the element-wise mapping of the logical input tensor elements (domain) to the Intel FPGA AI Suite IP input tensor format (co-domain) described earlier.

The transform mapping file has columns that correspond to the offset and subscript indices for the logical input tensor elements, and the corresponding elements in the transformed Intel® FPGA AI Suite input tensor.
For a graph with the input example given in Input Tensor In-Memory Layout, the transform mapping CSV output from the DLA compiler would be as follows:
Table 6.  Example Transform Mapping CSV Output
Logical Tensor Offset Input Channel (C) Input Depth (D) Input Height (H) Input Width (W) → Input Tensor Offset Transformed Channel (C) Transformed Depth (D) Transformed Height (H) Transformed Width (W) Transformed C-vector (Cvec)
0 0 0 0 0 → 0 0 0 0 0 0
1 0 0 0 1 → 2 0 0 0 1 0
2 0 0 1 0 → 4 0 0 1 0 0
3 0 0 1 1 → 6 0 0 1 1 0
4 1 0 0 0 → 1 1 0 0 0 0
5 1 0 0 1 → 3 1 0 0 1 0
6 1 0 1 0 → 5 1 0 1 0 0
7 1 0 1 1 → 7 1 0 1 1 0
8 2 0 0 0 → 8 0 0 0 0 1
9 2 0 0 1 → 10 0 0 0 1 1
10 2 0 1 0 → 12 0 0 1 0 1
11 2 0 1 1 → 14 0 0 1 1 1

The tensor offsets in this table are logical, not address offsets and are thus independent of data type. The transformation typically implicitly adds zero padding to the data. As such, not all transformed output logical offsets are mapped from a given input logical offset.

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