Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 12/01/2023
Public
Document Table of Contents
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2.5.3. AXI Interface Clock and Reset

Name

Clock

Reset

Note

DDR0 Initiator

ddr_clk

dla_resetn

N/A

CSR Responder

ddr_clk

dla_resetn

The CSR initiator operates on the ddr_clk clock.

Interrupt Initiator

irq_clk

dla_resetn

N/A

The following parameters are used by the AXI interfaces. The parameter values can be modified in the Architecture Description files as described in IP Generation Utility.

Name

Supported Value

Entry in Architecture Description

C_CSR_AXI_ADDR_WIDTH

11

= dma.csr_addr_width

C_CSR_AXI_DATA_WIDTH

32

= dma.csr_data_bytes * 8

C_DDR_AXI_ADDR_WIDTH

1~32

= dma.ddr_addr_width

C_DDR_AXI_BURST_WIDTH

1~8

= dma.ddr_burst_width

C_DDR_AXI_DATA_WIDTH

64, 128, 256, 512 (bits)

= dma.ddr_data_bytes * 8

C_DDR_AXI_THREAD_ID_WIDTH

2

= ddr_read_id_width