Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 12/01/2023
Public
Document Table of Contents
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2.5.2. AXI Interfaces

Name

Type

Description

DDR0 Initiator

AXI4

Initiator port for connecting to DDR memory

CSR Responder

AXI4-Lite

Exposes IP MMIO region

Interrupt Initiator

Interrupt Sender

Level sensitive interrupt