Intel® FPGA AI Suite: IP Reference Manual

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ID 768974
Date 4/05/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite IP Reference Manual 2. About the Intel® FPGA AI Suite IP 3. Intel® FPGA AI Suite IP Generation Utility 4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility 5. CSR Map and Descriptor Queue A. Intel® FPGA AI Suite IP Reference Manual Archives B. Intel® FPGA AI Suite IP Reference Manual Document Revision History
2. About the Intel® FPGA AI Suite IP x
2.1. Supported Models 2.2. Model Performance 2.3. Intel® FPGA AI Suite Layer / Primitive Ranges 2.4. Intel® FPGA AI Suite IP Block Configuration 2.5. IP Block Interfaces
2.1. Supported Models x
2.1.1. MobileNet V2 differences between Caffe and TensorFlow models
2.2. Model Performance x
2.2.1. Throughput on the MobileNetV1 model (and other very fast models)
2.4. Intel® FPGA AI Suite IP Block Configuration x
2.4.1. Architecture Description File Format for Instance Parameterization 2.4.2. Architecture Description File Parameters
2.4.2. Architecture Description File Parameters x
2.4.2.1. Parameter group: Global Parameters 2.4.2.2. Parameter group: activation 2.4.2.3. Parameter group: pe_array 2.4.2.4. Parameter group: pool 2.4.2.5. Module: softmax 2.4.2.6. Parameter group: dma 2.4.2.7. Parameter group: xbar Parameter: xbar/xbar_k_vector 2.4.2.8. Parameter group: filter_scratchpad 2.4.2.9. Parameter group: config_network
2.5. IP Block Interfaces x
2.5.1. Clock and Reset 2.5.2. AXI Interfaces 2.5.3. AXI Interface Clock and Reset 2.5.4. Input Feature Tensor In-Memory Format 2.5.5. Output Tensor In-Memory Format
2.5.4. Input Feature Tensor In-Memory Format x
2.5.4.1. Multiple Input Graphs 2.5.4.2. Input Folding 2.5.4.3. Input Scale and Shift 2.5.4.4. Input Transform Mapping
3. Intel® FPGA AI Suite IP Generation Utility x
3.1. IP Generation Utility Execution Flows 3.2. IP Generation Utility Inputs 3.3. IP Generation Utility Outputs 3.4. IP Generation Utility Command Line Options
3.4. IP Generation Utility Command Line Options x
3.4.1. The --flow create_ip Flow 3.4.2. The --flow add_arch Flow 3.4.3. The --flow list Flow 3.4.4. The --flow remove_arch Flow
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility x
4.1. Files Generated by the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.2. Building the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.3. Running the Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility 4.4. Intel® FPGA AI Suite Ahead-of-Time (AOT) Splitter Utility Example Application
5. CSR Map and Descriptor Queue x
5.1. Discovery ROM 5.2. Interrupt Control 5.3. DMA Descriptor Queue 5.4. DMA Control Registers 5.5. Performance Registers
1. Intel® FPGA AI Suite IP Reference Manual
2. About the Intel® FPGA AI Suite IP
3. Intel® FPGA AI Suite IP Generation Utility
4. Intel® FPGA AI Suite Ahead-of-Time Splitter Utility
5. CSR Map and Descriptor Queue
A. Intel® FPGA AI Suite IP Reference Manual Archives
B. Intel® FPGA AI Suite IP Reference Manual Document Revision History

2.4.2.7. Parameter group: xbar

For each layer of the graph, data passes through the convolution engine (referred to as the processing element [PE] array), followed by zero or more auxiliary modules. The auxiliary modules perform operations such as activation or pooling.

After the output data for a layer has been computed, it can be sent to one of the following places:

  • An internal buffer while waiting for the start of the next convolution layer.
  • The external memory for reading by the host program.

Internally, a crossbar (xbar) connects the modules together. The xbar parameters specify the connections between the PE array, the auxiliary modules, the input feeder (which holds data waiting for the next convolution layer), and the output writer (which writes the data to the external memory).

Consider the following example:

xbar {
	  xbar_k_vector : 16
	  max_input_interfaces : 4
	  max_output_interfaces : 4
	  xbar_ports {
	    xbar_aux_port {
	      name : 'activation'
	      input_connection : 'xbar_in_port'
	    }
	    xbar_aux_port {
	      name : 'pool'
	      input_connection : 'xbar_in_port'
	      input_connection : 'activation'
	    }
	  }
	  xbar_in_port {
	    external_connection  : 'pe_array'
	  }
	  xbar_out_port {
	    external_connection : 'input_feeder'
	    external_connection : 'output_writer'
	    input_connection    : 'xbar_in_port'
	    input_connection    : 'pool'
	  }
	}

The crossbar always has the following elements:

  • An xbar_in_port element that accepts the incoming connection from the PE array.
  • An xbar_out_port element that connects externally to the input feeder and output writer.

This example architecture also has two auxiliary modules defined with xbar_aux_port elements: a pool module and an activation module. The xbar_aux_port elements are specified in the xbar_ports section.

In this configuration, the activation module can accept data from the xbar_in_port (the PE array), while the pool module can accept data from the xbar_in_port or from the activation module.

Finally, the output port can accept data either directly from the xbar_in_port or from the pool module. These connections limit how data flows through the system.

In this example, the activation module cannot write out from the layer. Activations must be followed by pooling layers. Also, an activation layer cannot follow a pooling layer. However, the convolution can be followed by a pooling layer without an activation layer in between.

Connections cost area and can reduce fMAX. You can reduce area by including only the connections that are required for a given graph (sometimes called "depopulating" the crossbar). If you use this architecture as the starting point for the Architecture Optimizer, the result can improve throughput.

To see examples of other crossbar configurations, review the example_architectures/ directory.

Parameter: xbar/xbar_k_vector

This parameter defines the width of the interface into the crossbar. Typically, this parameter is set to be equal to the width of the widest interface into any of the auxiliary modules.

Typically, the architecture optimizer is used to set this parameter.

Legal values:
[2,4,8,16,32]
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