Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 4/05/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3. DMA Descriptor Queue

The DMA contains a single descriptor FIFO for enqueuing inference requests. Descriptors potentially require multiple register writes and are added to the queue upon writing to the desc_input_output_base_addr register.

The desc_cfg_filter_base_addr and desc_cfg_num_words are registers that hold their value.

If you already enqueued a DMA descriptor and want to enqueue another descriptor with the same values for the desc_cfg_filter_base_addr and desc_cfg_num_words registers, then write to the desc_input_output_base_addr register.

If you want to change the desc_cfg_filter_base_addr and desc_cfg_num_words registers for the next descriptor, then you must set new values before writing to the desc_input_output_base_addr register.

Table 13.  DMA Descriptor Queue Registers








Base address pointer for the configuration buffer and for the filter buffer.

The filters are located at desc_cfg_filter_base_addr + desc_cfg_num_words, which is encoded in the address provided to the filter reader as configuration data.

Must be aligned to a multiple of the DDR word size.

desc_cfg_num_words - 2



Length of the configuration buffer - 2, in config words (64 bits – 32 for instruction, 32 for data)




Base address pointer for the input feature data to be used for inference, and also the base address to place the output inference results into.

Must be aligned to a multiple of the DDR word size.

Writing to this register enqueues a descriptor into the internal DMA descriptor queue.




This register is useful for debugging. Production software should not need to read from this.

Bit 0: Asserts if the descriptor queue overflows; this is a sticky bit which only clears after reset.

Bit 1: Descriptor queue is full or almost full.

Bit 2: Asserts if the inference limit for an unlicensed IP is reached. When asserted, inference requests are rejected.

All other bits are reserved.