Intel® FPGA AI Suite: Getting Started Guide

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ID 768970
Date 9/06/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Getting Started Guide 2. Intel® FPGA AI Suite Components 3. Intel® FPGA AI Suite Installation Overview 4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools 5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites 6. Intel® FPGA AI Suite Quick Start Tutorial A. Intel® FPGA AI Suite Getting Started Guide Archives B. Intel® FPGA AI Suite Getting Started Guide Document Revision History
3. Intel® FPGA AI Suite Installation Overview x
3.1. Intel® FPGA AI Suite Directory Structure
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Intel® Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your Intel® FPGA AI Suite Installation
4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools x
4.3.1. Installing the Intel® FPGA AI Suite Into an Alternative Location
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex® 7 Devices 5.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices
6. Intel® FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. Intel® FPGA AI Suite Getting Started Guide
2. Intel® FPGA AI Suite Components
3. Intel® FPGA AI Suite Installation Overview
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites
6. Intel® FPGA AI Suite Quick Start Tutorial
A. Intel® FPGA AI Suite Getting Started Guide Archives
B. Intel® FPGA AI Suite Getting Started Guide Document Revision History

6.6. Programming the FPGA Device

To complete this section of the tutorial, you must have installed one of the following supported design examples:

  • PCIe-based design example for Intel® Arria® 10 devices

    This design example requires the Intel® Programmable Acceleration Card (PAC) with Intel® Arria® 10 GX FPGA board.

  • PCIe-based design example for Intel Agilex® 7 devices

    This design example requires the Terasic* DE10-Agilex Development Board.

For installation instructions, see Intel FPGA AI Suite Installation Overview.

Important: The instructions here assume that your machine has only a single board installed.

The PCIe-based design examples requires a runtime layer that must be compiled before the design is usable. The runtime for the design examples typically needs to be compiled only once. However, a new FPGA bitstream must be generated whenever any of the following parameters change:

  • Number of IP instances built in the design example.
    • PCIe-based design example for Intel® Arria® 10 devices supports 1 or 2 instances.
    • PCIe-based design example for Intel Agilex® 7 devices supports up to 4 instances.
  • Configuration of the IP architecture (as specified by a .arch file)
  • Quartus fitter seed (or any other "try-harder" compilation options)

Depending on your design example, follow the instructions in one of the following sections:

Programming the Intel Agilex® 7 Device ( Terasic* DE10-Agilex Development Board)

To program the DE10-Agilex-B2E2 board required by the PCIe-based design example for Intel Agilex® 7 devices:

  1. Build the runtime with the following commands:
    cd $COREDLA_WORK/runtime
rm -rf build_Release
./build_runtime.sh -de10_agilex
  2. Program the bitstream onto the FPGA device with the following commands:
    jtagdir=$COREDLA_WORK/runtime/build_Release/fpga_jtag_reprogram
bitsdir=$COREDLA_WORK/demo/bitstreams
$jtagdir/fpga_jtag_reprogram $bitsdir/AGX7_Performance.sof
curarch=$COREDLA_ROOT/example_architectures/AGX7_Performance.arch

The bitstream completely reprograms the board, which causes it to disconnect from the PCIe bus. The board is kept accessible with the $COREDLA_WORK/runtime/fpga_jtag_reprogram tool.

Precompiled bitstreams are provided in the $COREDLA_WORK/demo/bitstreams/ directory. Some bitstreams instantiate a large IP, while others instantiate a small IP. There are also differences in which bitstreams support which neural networks. For details, refer to the Intel® FPGA AI Suite IP Reference Manual .

Programming the Intel® Arria® 10 Device ( Intel® PAC with Intel® Arria® 10 GX FPGA)

To program the Intel® PAC with Intel® Arria® 10 GX FPGA hardware used by the PCIe-based design example for Intel® Arria® 10 devices:

  1. Build the runtime with the following commands:
    cd $COREDLA_WORK/runtime
rm -rf build_Release
./build_runtime.sh
  2. Program the bitstream onto the FPGA device with the following commands:
    fpgaconf -v $COREDLA_WORK/demo/bitstreams/A10_Performance.gbs
curarch=$COREDLA_ROOT/example_architectures/A10_Performance.arch

The bitstream contains only the AFU. In this case, the AFU consists of the Intel® FPGA AI Suite IP and some interface logic to connect it to the FIM. The FIM, which is the logic delivered as part of the BSP responsible for the interfaces like the memory interface and PCIe interface, is already on the FPGA device.

Precompiled bitstreams are provided in the $COREDLA_WORK/demo/bitstreams/ directory. Some bitstreams instantiate a large IP, while others instantiate a small IP. There are also differences in which bitstreams support which neural networks. For details, refer to the Intel® FPGA AI Suite IP Reference Manual .

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