AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs

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ID 764994
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Best Practices for Floorplanning Partial Reconfiguration Designs
2. Best Practices for Floorplanning Partial Reconfiguration Designs x
2.1. Document Prerequisites 2.2. Best Practice PR Design Techniques 2.3. Document Revision History of AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs
2.2. Best Practice PR Design Techniques x
2.2.1. Technique 1: Use Joint Periphery Placement Regions 2.2.2. Technique 2: Lock Down the Periphery Elements 2.2.3. Technique 3: Reduce Data Connections Across Logic Lock Boundaries 2.2.4. Technique 4: Lock Down PR Boundary Ports
1. Answers to Top FAQs
2. Best Practices for Floorplanning Partial Reconfiguration Designs

2.2.1. Technique 1: Use Joint Periphery Placement Regions

For optimum performance, carefully floorplan your design to ensure that you place the periphery together as close as possible. In PR designs, you preserve the periphery IPs in the static region. When compiling a project without any Logic Lock region constraints, the Compiler normally places the periphery logic adjacent to the related hard IP components, as Floorplan 1 shows in Figure 1: Use Joint Placement Regions.

Figure 2. Use Joint Placement Regions


Floorplan 1 shows the floorplan without Logic Lock constraints. Floorplan 2 shows some initial Logic Lock region constraints that reserve the areas adjacent to the hard elements for the static regions. However, Floorplan 2 Logic Lock constraints are sub-optimal because they are disjointed areas forming non-convex regions. Such regions restrict the Intel® Quartus® Prime Fitter's ability to place the design optimally.

For example, when there is a path from point A to B in Floorplan 2, the optimum performance routing is:

  1. The path crosses the PR boundary (exiting the PR region).
  2. The path crosses the static region.
  3. The path re-enters the PR boundary to reach the destination (entering PR region).

The disjointed Logic Lock placement regions further burden the highly utilized static region, especially if you do not plan the PR routing region constraint. Because the Fitter cannot estimate the implementation of different personas, inconsistent results can occur for different PR persona implementations.

If you reserve the routing in the PR region, the path from point A has to at least travel along the PR boundary to arrive at point B in Floorplan 2. This long routing has a negative impact on the design performance. The same condition applies for the path from point C to D in Floorplan 2. From point C to D the routing must cross the PR region. The PR region crossing negatively affects the performance of the PR implementation revision. The Fitter generally labors to fit non-convex placement regions. A disjointed region is an extreme example of a non-convex placement region.

To mitigate the impact of such regions, carefully floorplan to place the periphery together as close as possible to the location of the hard IP (PCIe on the left, Ethernet on the right) For example, you can combine the two disjointed regions for the two PCIe periphery elements by defining a thinner Logic Lock constraint area, as Floorplan 3 shows. You can also join the place region for the Ethernet periphery logic to the bottom EMIF logic.

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