AN 992: Best Practices for Floorplanning Partial Reconfiguration Designs

ID 764994
Date 2/21/2023

1. Answers to Top FAQs

Updated for:
Intel® Quartus® Prime Design Suite 22.4

What is partial reconfiguration (PR)?


What prerequisites are there?

Document Prerequisites

What limits PR design performance?

Best Practice PR Design Techniques

How do I floorplan for PR?

Use Joint Periphery Placement Regions

How do I constrain the periphery?

Lock Down Periphery Elements

How do I improve PR persona performance?

Lock Down PR Boundary Ports

What are the known issues?

Intel FPGA Support Forums: PR

Do you have training on PR?

Intel FPGA Technical Training Catalog