HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 7/20/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10
5. HDMI RX PHY x
5.1. Architecture 5.2. Dynamic Reconfiguration 5.3. IP Ports 5.4. IP Configuration Parameters 5.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. Architecture 6.2. Dynamic Reconfiguration 6.3. IP Ports 6.4. IP Configuration Parameters 6.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX Only and TX Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

6.3. IP Ports

Table 22.  HDMI TX PHY Intel FPGA IP Ports
Interface Port Type Clock Domain Port Direction Description
mgmt_clk Clock mgmt_clk Input Free-running system clock input (100 MHz)
fr_clk Clock fr_clk Input Free-running clock for the transceiver power-up calibration - 61-800 MHz.
tx_tmds_clk Clock tx_tmds_clk Input This clock frequency follows the TMDS clock frequency.
tx_serial_data Conduit tx_tmds_clk tx_serial_data [3:0] Input HDMI serial TX data stream
reset Reset reset Input Main asynchronous reset
irq Interrupt mgmt_clk irq Output Interrupt signal - reserved for future use (not currently supported)
phy_interface Conduit - tx_clk Output Transceiver parallel clock
- vid_clk Output Synchronous video clock
- ls_clk Output Link speed clock
tx_clk tx_parallel_data [79:0] Output Tx parallel data. 20 Bits per transceiver.
mgmt_clk in_lock Output Indicates transceivers are all locked.
mgmt_clk os Input ‘0’ = > rx_parallel_data is not oversampled. ‘1’ => oversampling ratio of 5.
av_mm_control Avalon MM mgmt_clk av_mm_control_write Input Avalon memory-mapped interface for control of the IP core.
mgmt_clk av_mm_control_read Input
mgmt_clk av_mm_control_address Input
mgmt_clk av_mm_control_writedata Input
mgmt_clk av_mm_control_readdata Output
mgmt_clk av_mm_control_waitrequest Output
txphy_rcfg_master Avalon MM mgmt_clk txphy_rcfg_master_write Output Avalon memory-mapped interface for reconfiguration of the transceivers – connects to the PHY Arbiter.
mgmt_clk txphy_rcfg_master_read Output

Avalon memory-mapped interface for reconfiguration of the transceivers – connects to the PHY Arbiter.

Only valid when SEPARATE_RCFG_INTF_EN = 0.
mgmt_clk txphy_rcfg_master_address [9:0] Output
mgmt_clk txphy_rcfg_master_writedata [31:0] Output
mgmt_clk txphy_rcfg_master_readdata [31:0] Input
mgmt_clk txphy_rcfg_master_waitrequest Input
txphy_rcfg_slave Conduit mgmt_clk txphy_rcfg_slave_write [3:0] Input

4x Avalon memory-mapped interface with extra signals for reconfiguration of the transceivers – connects to the PHY Arbiter.

txphy_reconfig_en signals to the PHY arbiter that that the TX PHY requires access to the transceivers.

txphy_cal_busy signals from each transceiver that a calibration is in progress.

txphy_reconfig_cal_busy signals back from the PHY Arbiter that the transceiver is undergoing calibration or reconfiguration.

txphy_rcfg_slave_chan indicates which transceiver is to be accessed.

Only valid when SEPARATE_RCFG_INTF_EN = 0
mgmt_clk txphy_rcfg_slave_read [3:0] Input
mgmt_clk txphy_rcfg_slave_address [39:0] Input
mgmt_clk txphy_rcfg_slave_writedata [127:0] Input
mgmt_clk txphy_rcfg_slave_readdata [127:0] Output
mgmt_clk txphy_rcfg_slave_waitrequest [3:0] Output
mgmt_clk txphy_reconfig_en Output
mgmt_clk txphy_cal_busy [3:0] Input
mgmt_clk txphy_reconfig_cal_busy [3:0] Output
mgmt_clk txphy_rcfg_slave_chan [1:0] Output
txphy_rcfg_master_# Avalon MM mgmt_clk txphy_rcfg_master_write_# Output Avalon memory-mapped interfaces for reconfiguration of the transceivers – connects to the PHY Arbiter- one for each channel (indicated by #). Only valid when SEPARATE_RCFG_INTF_EN = 1.
mgmt_clk txphy_rcfg_master_read_# Output
mgmt_clk txphy_rcfg_master_address_# [9:0] Output
mgmt_clk txphy_rcfg_master_writedata_# [31:0] Output
mgmt_clk txphy_rcfg_master_readdata_# [31:0] Input
mgmt_clk txphy_rcfg_master_waitrequest_# Input
txphy_rcfg_slave_#(# values 2:0) Conduit mgmt_clk txphy_rcfg_slave_write_# Input

Avalon memory-mapped interface with extra signals for reconfiguration of the transceivers – connects to the PHY Arbiter – one for each transceiver channel.

txphy_reconfig_en_# signals to the PHY arbiter that that the TX PHY requires access to the transceivers.

txphy_cal_busy_# signals from each transceiver that a calibration is in progress.

txphy_reconfig_cal_busy_# signals back from the PHY Arbiter that the transceiver is undergoing calibration or reconfiguration.

Only valid when SEPARATE_RCFG_INTF_EN = 1.
mgmt_clk txphy_rcfg_slave_read_# Input
mgmt_clk txphy_rcfg_slave_address_# [9:0] Input
mgmt_clk txphy_rcfg_slave_writedata_# [31:0]  
mgmt_clk txphy_rcfg_slave_readdata_# [31:0] Output
mgmt_clk txphy_rcfg_slave_waitrequest_# Output
  txphy_reconfig_en_# Output
  txphy_cal_busy_# Output
  txphy_reconfig_cal_busy_# Input
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