HDMI PHY Intel FPGA IP User Guide

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ID 732147
Date 7/20/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI PHY Intel® FPGA IP Quick Reference 2. HDMI PHY Overview 3. HDMI PHY Intel® FPGA IP Getting Started 4. HDMI Hardware Design Examples 5. HDMI RX PHY 6. HDMI TX PHY 7. PHY Arbiter and Transceiver Merging 8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide
2. HDMI PHY Overview x
2.1. Release Information 2.2. Device Family Support 2.3. Feature Support 2.4. Resource Utilization
3. HDMI PHY Intel® FPGA IP Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel FPGA IP Evaluation Mode
4. HDMI Hardware Design Examples x
4.1. HDMI Hardware Design Examples for Intel® Arria® 10
5. HDMI RX PHY x
5.1. Architecture 5.2. Dynamic Reconfiguration 5.3. IP Ports 5.4. IP Configuration Parameters 5.5. RX PHY Address Map
6. HDMI TX PHY x
6.1. Architecture 6.2. Dynamic Reconfiguration 6.3. IP Ports 6.4. IP Configuration Parameters 6.5. TX PHY Address Map
7. PHY Arbiter and Transceiver Merging x
7.1. PHY Arbiter IP Ports 7.2. IP Configuration Parameters 7.3. PHY Merging and Arbiter Connection
7.3. PHY Merging and Arbiter Connection x
7.3.1. RX Only and TX Only Use Cases 7.3.2. Single RX and TX Simple Merge 7.3.3. Complex Straddled Channels
1. HDMI PHY Intel® FPGA IP Quick Reference
2. HDMI PHY Overview
3. HDMI PHY Intel® FPGA IP Getting Started
4. HDMI Hardware Design Examples
5. HDMI RX PHY
6. HDMI TX PHY
7. PHY Arbiter and Transceiver Merging
8. Document Revision History for the HDMI PHY Intel FPGA IP User Guide

7.3.3. Complex Straddled Channels

Typically, in complex configurations and closely pack transceivers, the PHY Arbiter and the TX and RX PHYs split out the reconfiguration interface so that each transceiver channel has its own conduit.

This is shown in the following figure.

Figure 12. RX PHY and PHY Arbiter with Separate Reconfiguration Interfaces

This is useful in more complex designs where, for example TX and RX do not align – i.e. TX 0 might not correspond to RX 0. This might be a result of tightly packing RX and TX channels. An example is shown in the following figure. In this example, separate reconfiguration interfaces and multiple arbiters are required and the channel numbers are not one-to-one. Note the following key points on this setup:

  • Arbiter1 has one channel but handles TX0[3] and RX1[0]
  • Arbiter2 has two channels: Arbiter2 channel 0 connects TX1 channel 0 and RX1 channel 1
  • Arbiter3 is two channels but TX only
Figure 13. Overlapping HDMI Channels Requiring multiple PHY Arbiters

The physical location constraints (i.e. pins) must also correspond to this. In addition the XCVR_RECONFIG_GROUP constraints must be set in the projects .qsf file (or in the assignment editor). 

set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to rx1 [2]
set_instance_assignment -name XCVR_RECONFIG_GROUP 5 -to tx1 [1]
set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to rx1 [1]
set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to tx1 [0]
set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to rx1 [0]
set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to tx0 [3]
set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to rx0 [2]
set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to tx0 [2]
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to rx0 [1]
set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx0 [1]
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to rx0 [0]
set_instance_assignment -name XCVR_RECONFIG_GROUP 0 -to tx0 [0]
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