F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Release Notes

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ID 726811
Date 4/01/2024
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1. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Release Notes
1. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Release Notes x
1.1. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v4.1.0 1.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v4.0.0 1.3. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v3.0.0 1.4. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v2.0.4 1.5. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v2.0.3 1.6. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v2.0.2 1.7. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v2.0.1 1.8. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v2.0.0 1.9. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v1.0.0 1.10. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
1. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Release Notes

1.1. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP v4.1.0

Table 1.  v4.1.0 2024.04.01
Quartus® Prime Pro Edition Version Description Impact
24.1

Fixed bug related to soft CSR reset acknowledge read back in the datapath Avalon® memory-mapped interface (reconfig_pdp).

You must regenerate the IP if you are using the soft CSR registers for reset and reset acknowledgment.
Added Agilex™ 9 device family support. —

Some Intel® FPGA IP products that previously included a Nios® II processor now use a Nios® V processor.

If you do not have a valid Nios® V license, you might receive an error message when you generate programming files for a design that includes these Intel® FPGA IP products.

For details and a workaround, refer to Why do I get an error in generating programming files and it shows as invalid license for Nios® V Processor for Intel® FPGA in the Quartus® Prime Pro Edition software version 24.1? in the Intel® FPGA Knowledge Base.

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