F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

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Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles 3.3. Generating IP-XACT File
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP reconfiguration soft CSR registers are only present in the 1st fracture.

The example below shows you how to set the reconfiguration soft CSR registers for address 20'h820 - 828 for a given Reconfiguration subset mode. The following example is for Reconfiguration group of 100G-4 Reconfigurable. Refer to F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Reconfiguration Soft CSR Registers for more details about these registers.
Table 37.  Example for Reconfiguration group: 100G-4, Fracture Count = 4 and PMA Lane Count = 4
Reconfiguration Subset - FEC Mode 100G-4-FEC

50G-2-FEC,

50G-2

25G-1-FEC,

25G-1-FEC,

25G-1,

25G-1
Reconfiguration Soft CSR Subset Mode and Register Settings
Byte Address 3 Register Name
20'h820 Fracture Count 1 2 4
PMA count per Fracture 4 2 1
Rate per PMA 25G 25G 25G
20'h824 FEC Mode Enabled Fracture 7-0 28'h0, 4'h2 28'h0, 4'h2 24'h0, 4'h2, 4'h2
20'h828 FEC Mode Enabled Fracture 12-8 32'b0 32'b0 32'b0
Note: The example above enables FEC mode: IEEE 802.3 RS(528,514) (CL 91,KR)
The following table describes all the reconfiguration soft CSR registers for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP.
Table 38.  F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Reconfiguration Soft CSR Registers
Byte Address3[19:0] Bit Offset Name Description Access Value after Reset
20’h820 [13:9] fracture_cnt

5’d1 -1 Fracture

5’d2 -2 Fractures

5’d3 -3 Fractures

5’d4 -4 Fractures

5’d6 -6 Fractures

5’d8 -8 Fractures

5’d12 -12 Fractures

 Read-write Reflects startup profile value
[8:4] pma_cnt_per_fracture

5’d1 -1 PMA lane

5’d2 -2 PMA lanes

5’d4 -4 PMA lanes

5’d6 -6 PMA lanes

5’d8 -8 PMA lanes

5’d12 -12 PMA lanes

5’d16 -16 PMA lanes

 Reflects startup profile value
[3:0] rate_per_pma 4’d1 -25G

4’d2 -50G

4’d3 -100G

 Reflects startup profile value
20’h824 [31:28] fec_mode_frac7

FEC mode for fracture7

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Read-write Reflects startup profile value
[27:24] fec_mode_frac6

FEC mode for fracture6

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[23:20] fec_mode_frac5

FEC mode for fracture5

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[19:16] fec_mode_frac4

FEC mode for fracture4

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[15:12] fec_mode_frac3

FEC mode for fracture3

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[11:8] fec_mode_frac2

FEC mode for fracture2

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[7:4] fec_mode_frac1

FEC mode for fracture1

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[3:0] fec_mode_frac0

FEC mode for fracture0

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value

20’h828

 [31:16] Reserved Reserved Read-write 0x0
[15:12] fec_mode_frac11

FEC mode for fracture11

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4- Ethernet Consortium RS(528,514)

4’d5- Ethernet Consortium RS(544,514)

4’d6- Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[11:8] fec_mode_frac10

FEC mode for fracture10

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4 - Ethernet Consortium RS(528,514)

4’d5 - Ethernet Consortium RS(544,514)

4’d6 - Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[7:4] fec_mode_frac9

FEC mode for fracture9

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258

4’d4 - Ethernet Consortium RS(528,514)

4’d5 - Ethernet Consortium RS(544,514)

4’d6 - Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value
[3:0] fec_mode_frac8

FEC mode for fracture8

4’d0 - Disable

4’d1- IEEE 802.3 RS(528,514) (CL 91,KR)

4’d2- IEEE 802.3 RS(544,514) (CL 91,KP)

4’d3- Ethernet Tech. Cons. LL RS(272,258)

4’d4 - Ethernet Consortium RS(528,514)

4’d5 - Ethernet Consortium RS(544,514)

4’d6 - Interlaken RS(544,514)

4’d7 -FC RS(544,514)

4’d8 -FC RS(528,514)

4’d9- FlexO RS(544,514)

4’d10- FlexO RS(528,514)

4’d11:15- Reserved

 Reflects startup profile value

20’h82C

 [3] fec_enable_err For example, trying to enable 5th fracture in a 2 fracture reconfiguration group is an error. Read-only 0x0
[2] rate_per_pma_err For example if a reconfiguration group does not have 100G base transceiver rate but write to this register happens for 100G, that is an error 0x0
[1] pma_cnt_per_fracture_err For example, if a reconfiguration group does not have 4 transceiver fractures, but value written to this register indicates 4, that is an error. 0x0
[0] fracture_cnt_err For example if a reconfiguration group has at the most 4 sub-fractures, but value written indicates 8, that is an error. 0x0
3
4 The physical Avalon Memory-Mapped Interface(AVMM) is based on 32-bit word addresses. However this document refers to the registers as byte addresses, you can convert to word addresses by shifting 2 bits to the right (divide by 4). You can use a byte enabled signal to address individual byes.
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