F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
ID
720989
Date
11/29/2023
Public
1. About the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
2. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Archive
9. Document Revision History for the F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP
3.2. Installing and Licensing Intel® FPGA IPs
3.3. Specifying the IP Core Parameters and Options
3.4. Generated File Structure
3.5. Simulating Intel® FPGA IPs
3.6. Upgrading the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core
3.7. Integrating Your IP Core in Your Design
3.7.1. Adding the F-Tile Reference and System PLL IP
Figure 6. 1G/2.5G/5G/10G Multirate Ethernet PHY Interface with F-tile Reference and System PLL Clocks IP
You must connect the F-Tile Reference and System PLL Clocks Intel® FPGA IP to the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP to compile the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP successfully.
The F-Tile Reference and System PLL Clock Intel® FPGA IP configures the reference and system clocks of the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
For more information, refer to Reference and System PLL Clock for your IP Design in the F-Tile Ethernet Intel FPG Hard IP User Guide.
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