F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

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ID 720987
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware 2.5. Signal Tap Debugging
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
2.5. Signal Tap Debugging x
2.5.1. Signal Tap Debug Signals
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.3.3. Reset Scheme x
3.3.3.1. Reset Sequence
3.3.3.1. Reset Sequence x
3.3.3.1.1. Run-time Reset Sequence—TX 3.3.3.1.2. Run-time Reset Sequence—RX 3.3.3.1.3. Run-time Reset Sequence—TX + RX
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure 3.5.2. Design Constraints
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface 4.6. IEEE 1588v2 Timestamp Interface Signals 4.7. Packet Classifier Interface Signals 4.8. TOD Interface Signals
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY 5.4. TOD
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multirate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.3.1
IP Version 22.3.1
This user guide provides the features, architecture description, steps to instantiate, and guidelines about the design examples for the Low Latency Ethernet 10G MAC Intel® FPGA IP using the Agilex™ 7 (F-Tile) devices.

Intended Audience

This document is intended for:

  • Design architect to make IP selection during system level design planning phase
  • Hardware designers when integrating the IP into their system level design
  • Validation engineers during system level simulation and hardware validation phase

Related Documents

The following table lists other reference documents which are related to the Low Latency Ethernet 10G MAC Intel® FPGA IP.
Table 1.  Related Documents
Reference Description
F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines about the Low Latency Ethernet 10G MAC Intel® FPGA IP for Agilex™ 7 (F-Tile) devices.
Low Latency Ethernet 10G MAC Intel® FPGA IP Release Notes Lists the changes made for the Low Latency Ethernet 10G MAC Intel® FPGA IP in a particular release.
F-Tile 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines about the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 7 (F-Tile) devices.
F-Tile Ethernet Intel® FPGA Hard IP User Guide Provides the features, architecture description, steps to instantiate, and guidelines about the F-Tile Ethernet Intel® FPGA Hard IP.
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Agilex™ 7 F-Series and I-Series devices.

Acronyms and Glossary

Table 2.  Acronym List
Acronym Expansion
ALM Adaptive Logic Element
CRC Cyclic redundancy code
DIC Deficit idle count
IPG Inter-packet gap
CSR Control and Status Register
FPGA Field Programmable Gate Array
LAB Logic Array Block
LUT Look-up table
MAC Media Access Control
MLAB Memory Logic Array Block
PCS Physical coding sublayer
PFC Priority-based flow control
PHY Physical layer
PLL Phase-locked loop
PMA Physical medium attachment
VLAN Virtual local area network
PTP Precision Time Protocol
Level Two Title