F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

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ID 720987
Date 4/01/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case
3.5. Hardware Testing x
3.5.1. Test Procedure
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

2.3.2. Testbench

Figure 4. Block Diagram of the Testbench
Table 5.  Testbench Components
Component Description
Device under test (DUT) The design example.
Avalon® driver Consists of Avalon® streaming master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon® memory-mapped interface of the DUT.
Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulator console.
Level Two Title