F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
                    
                        ID
                        720987
                    
                
                
                    Date
                    4/01/2022
                
                
                    Public
                
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                        1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
                    
                
                    
                        2. Quick Start Guide
                    
                    
                
                    
                        3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
                    
                    
                
                    
                        4. Interface Signals Description
                    
                    
                
                    
                        5. Configuration Registers Description
                    
                    
                
                    
                    
                        6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
                    
                
            
        4. Interface Signals Description
Use the following tables to find the description of the signals in the design example. The pinout diagram for each design example specifies the width of the signals.