F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

Download PDF
ID 720987
Date 4/01/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 4. Interface Signals Description 5. Configuration Registers Description 6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design 2.3. Compiling and Simulating the Design 2.4. Compiling and Testing the Design in Hardware
2.2. Generating the Design x
2.2.1. Procedure 2.2.2. Design Example Parameters
2.3. Compiling and Simulating the Design x
2.3.1. Procedure 2.3.2. Testbench
2.4. Compiling and Testing the Design in Hardware x
2.4.1. Procedure 2.4.2. Hardware Setup
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case
3.5. Hardware Testing x
3.5.1. Test Procedure
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
4. Interface Signals Description
5. Configuration Registers Description
6. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide

4.3. Avalon® Streaming Interface Signals

Table 11.   Avalon® Streaming Interface Signals
Signal Direction Width Description
avalon_st_tx_startofpacket[] In [NUM_CHANNELS] Assert this signal to indicate the beginning of the TX data.
avalon_st_tx_endofpacket[] In [NUM_CHANNELS] Assert this signal to indicate the end of the TX data.
avalon_st_tx_valid[] In [NUM_CHANNELS] Assert this signal to indicate that the avalon_st_tx_data signal and other signals on this interface are valid.
avalon_st_tx_ready[] Out [NUM_CHANNELS] When asserted, indicates that the MAC IP is ready to accept data. The reset value of this signal is nondeterministic.
avalon_st_tx_error[] In [NUM_CHANNELS] Assert this signal to indicate that the current TX packet contains errors.
avalon_st_tx_data[][] In [NUM_CHANNELS][m] TX data from the client.

m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32.

avalon_st_tx_empty[][] In [NUM_CHANNELS][m] Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data.

m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2.

  • 0x0—All bytes are valid.
  • 0x1—The last byte is invalid.
  • 0x2—The last two bytes are invalid.
  • 0x3—The last three bytes are invalid.
avalon_st_rx_startofpacket[] Out [NUM_CHANNELS] When asserted, indicates the beginning of the RX data.
avalon_st_rx_endofpacket[] Out [NUM_CHANNELS] When asserted, indicates the end of the RX data.
avalon_st_rx_valid[] Out [NUM_CHANNELS] When asserted, indicates that the avalon_st_rx_data signal and other signals on this interface are valid.
avalon_st_rx_ready[] In [NUM_CHANNELS] Assert this signal when the client is ready to accept data.
avalon_st_rx_error[][] Out [NUM_CHANNELS][6] When set to 1, the respective bits indicate an error type:
  • Bit 0—PHY error.
    • The data on xgmii_rx_data contains a control error character (FE).
  • Bit 1—CRC error. The computed CRC value does not match the CRC received.
  • Bit 2—Undersized frame. The receive frame length is less than 64 bytes.
  • Bit 3—Oversized frame. The receive frame length is more than MAX_FRAME_SIZE.
  • Bit 4—Payload length error. The actual frame payload length is different from the value in the length/type field.
  • Bit 5—Overflow error. The receive FIFO buffer is full while it is still receiving data from the MAC IP.
avalon_st_rx_data[][] Out [NUM_CHANNELS][m] RX data to the client.

m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32.

avalon_st_rx_empty[][] Out [NUM_CHANNELS][m] Contains the number of empty bytes during the cycle that contain the end of the RX data.

m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2.

avalon_st_txstatus_valid[] Out [NUM_CHANNELS]

When asserted, this signal qualifies the avalon_st_txstatus_data and avalon_st_txstatus_error signals.

avalon_st_txstatus_data[][] Out [NUM_CHANNELS][40]

Contains information about the TX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_txstatus_error[][] Out [NUM_CHANNELS][7]

When set to 1, the respective bit indicates the following error type in the TX frame:

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.

The error status is invalid when an overflow occurs.
avalon_st_rxstatus_valid[] Out [NUM_CHANNELS] When asserted, this signal qualifies the avalon_st_rxstatus_data and avalon_ st_rxstatus_error signals.

The MAC IP asserts this signal in the same clock cycle the avalon_st_rx_ endofpacket signal is asserted.

avalon_st_rxstatus_data[][] Out [NUM_CHANNELS][40]

Contains information about the RX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame.
  • Bit 33: When set to 1, indicates a VLAN frame.
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[][] Out [NUM_CHANNELS][7]

When set to 1, the respective bit indicates the following error type in the RX frame.

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: Client error.
  • Bit 6: Unused.

The error status is invalid when an overflow occurs.
avalon_st_pause_data[][] In [NUM_CHANNELS][2] This signal takes effect when the register bits, tx_pauseframe_enable[2:1], are both set to the default value 0. Set this signal to the following values to trigger the corresponding actions.
  • 0x0—Stops pause frame generation.
  • 0x1—Generates an XON pause frame.
  • 0x2—Generates an XOFF pause frame. The MAC IP sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3—Reserved.
Level Two Title