F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

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ID 720985
Date 4/18/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide 2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 3. Getting Started 4. Functional Description 5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters 6. Interface Signals 7. Configuration Registers 8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives 9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
2.1. Release Information 2.2. Features 2.3. Low Latency Ethernet 10G MAC Operating Modes 2.4. Device Family Support 2.5. Performance and Resource Utilization
2.5. Performance and Resource Utilization x
2.5.1. Resource Utilization 2.5.2. TX and RX Latency
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 3.4. Generated File Structure 3.5. Simulating Intel® FPGA IP Cores 3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
3.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
3.6.1. Design Considerations
3.6.1. Design Considerations x
3.6.1.1. Timing Constraints
3.6.1.1. Timing Constraints x
3.6.1.1.1. Pseudo-Static CSR Fields 3.6.1.1.2. Clock Crosser 3.6.1.1.3. Dual Clock FIFO
3.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Agilex™ 7 Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. TX Promiscuous (Transparent) Mode 4.4.8. TX Timing Diagrams
4.4.4. XGMII Encapsulation x
4.4.4.1. Transmit Path
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. CRC and Padding Bytes Removal 4.5.6. Frame Length Checking 4.5.7. Overflow Handling 4.5.8. RX Promiscuous (Transparent) Mode 4.5.9. RX Timing Diagrams
4.5.3. Address Checking x
4.5.3.1. Unicast Frame Filtering 4.5.3.2. Multicast Frame Filtering
4.5.4. Frame Type Checking x
4.5.4.1. Malformed RX Packets 4.5.4.2. CRC Error 4.5.4.3. Address Check Error
4.5.6. Frame Length Checking x
4.5.6.1. Frame Length 4.5.6.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Avalon® Memory-Mapped Interface Programming Signals 6.5. Avalon® Streaming Data Interfaces 6.6. Avalon® Streaming Flow Control Signals 6.7. Avalon® Streaming Status Interface 6.8. PHY-side Interfaces 6.9. IEEE 1588v2 Interfaces
6.5. Avalon® Streaming Data Interfaces x
6.5.1. Avalon® Streaming TX Data Interface Signals 6.5.2. Avalon® Streaming RX Data Interface Signals 6.5.3. Avalon® Streaming Data Interface Clocks
6.7. Avalon® Streaming Status Interface x
6.7.1. Avalon® Streaming Interface TX Status Signals 6.7.2. Avalon® Streaming Interface RX Status Signals
6.8. PHY-side Interfaces x
6.8.1. XGMII TX Signals 6.8.2. XGMII RX Signals
6.9. IEEE 1588v2 Interfaces x
6.9.1. IEEE 1588v2 Egress TX Signals 6.9.2. IEEE 1588v2 Ingress RX Signals 6.9.3. IEEE 1588v2 Interface Clocks
7. Configuration Registers x
7.1. Register Map 7.2. Register Access Definition 7.3. Primary MAC Address 7.4. TX Configuration and Status Registers 7.5. Flow Control Registers 7.6. RX Configuration and Status Registers 7.7. ECC Registers 7.8. Statistics Registers 7.9. Timestamp Registers
7.9. Timestamp Registers x
7.9.1. Calculating PHY Total Latency 7.9.2. Calculating Deterministic Latency 7.9.3. PTP Register Configuration
1. About the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
2. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
3. Getting Started
4. Functional Description
5. Low Latency Ethernet 10G MAC Intel® FPGA IP Parameters
6. Interface Signals
7. Configuration Registers
8. F-Tile Low Latency Ethernet 10G MAC Intel FPGA IP User Guide Archives
9. Document Revision History for the F-Tile Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

7.9. Timestamp Registers

The TX and RX timestamp registers are available when you turn on the Enable time stamping parameter. Otherwise, these registers are reserved.
Table 41.  Timestamp Registers
Word Offset Register Name Description Access HW Reset Value
0x0100 tx_period_10G Specifies the clock period for the timestamp adjustment on the datapaths. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
  • Bits 0 to 15—period in fractional nanoseconds.
  • Bits 16 to 19—period in nanoseconds.
The default value is 3.2 ns for 312.5 MHz clock. Configure this register before you enable the MAC IP core for operations. 		RW 0x33333
0x0102 tx_adj_fns_10G Static timing adjustment in fractional nanoseconds on the transmit datapaths.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
 RW 0x0
0x0104 tx_adj_ns_10G Static timing adjustment in nanoseconds on the transmit datapaths.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 23—reserved. Set these bits to 0.
 RW 0x0
0x110 tx_asymmetry Specifies the asymmetry value and direction of arithmetic operation.
  • Bits 0 to 16—asymmetry value.
  • Bit 17—direction.
    • Set to 0—add asymmetry value to correction field (CF).
    • Set to 1—minus asymmetry value from CF.
  • Bit 18—enable bit.
 RW 0x0
0x112 tx_p2p

Specifies the direction of arithmetic operation for meanPathDelay.

  • Bit 0— direction.
    • Set to 0—add meanPathDelay value to CF.
    • Set to 1—minus meanPathDelay value from CF.
RW 0x0
0x114 tx_cf_err_stat
  • Bits 0—error status bit to indicate that ingress correction field is equal to the absolute maximum, 64’h7FF_FFFF_FFFF_FFFF.
  • Bit 16—error status bit to indicate that egress correction field is equal or larger than absolute maximum, 64’h7FFF_FFFF_FFFF_FFFF.
  • Bit 17—error status bit to indicate that residence time is equal or larger than 4 seconds.
  • Bit 18—error status bit to indicate that residence time is a negative value.
 RW1C 0x0
0x0120 rx_period_10G Specifies the clock period for the timestamp adjustment on the datapaths. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
  • Bits 0 to 15—period in fractional nanoseconds.
  • Bits 16 to 19—period in nanoseconds.
The default value is 3.2 ns for 312.5 MHz clock. 		RW 0x33333
0x0122 rx_adj_fns_10G Static timing adjustment in fractional nanoseconds on the receive datapaths.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
 RW 0x0
0x0124 rx_adj_ns_10G Static timing adjustment in nanoseconds on the receive datapaths.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 23—reserved. Set these bits to 0.
 RW 0x0
0x12E rx_p2p_mpd_ns

meanPathDelay valid and value in ns.

The peer-to-peer mechanism delivers meanPathDelay for each ingress port. This needs to be added to the Sync packet’s correction field before the packet is sent out on egress port. Thus, the egress port might add any of the ingress ports' 'meanPathDelay'. The value to be added at the egress port should correspond to the ingress port on which the Sync packet has arrived.

  • Bit 30—Indicates meanPathDelay is valid.
  • Bits 0 to 29—meanPathDelay value in nanosecond.
RW 0x0
0x130 rx_p2p_mpd_fns

meanPathDelay value in fns.

  • Bits 0 to 15—meanPathDelay value in fractional nanosecond.
RW 0x0

Section Content
Calculating PHY Total Latency
Calculating Deterministic Latency
PTP Register Configuration

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