F-Tile Ethernet Multirate Intel® FPGA IP User Guide

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ID 714307
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
1. Introduction x
1.1. Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation 1.7. F-Tile Ethernet Multirate IP Core Features and Constraints 1.8. F-Tile Ethernet Multirate IP Core Concepts
1.8. F-Tile Ethernet Multirate IP Core Concepts x
1.8.1. Reconfiguration Group 1.8.2. Base Profile 1.8.3. Secondary Profile 1.8.4. Secondary Profile Group 1.8.5. Startup Profile 1.8.6. Supported Reconfiguration Groups 1.8.7. PTP Timestamp Accuracy Support 1.8.8. Transceiver Lane Mapping
2. Interface Overview x
2.1. Port Numbering Scheme 2.2. Clock Signals 2.3. Reset Signals 2.4. Fractured MAC Segmented Interface for FGT Transceivers 2.5. Fractured MAC Segmented Interface for FHT Transceivers 2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers 2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers 2.8. Fractured MII PCS-Only Interface for FGT Transceivers 2.9. Fractured MII PCS-Only Interface for FHT Transceivers 2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers 2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers 2.12. MAC Flow Control Interface 2.13. Status Interface 2.14. Deterministic Latency Interface 2.15. Avalon® Memory-Mapped Reconfiguration Interfaces 2.16. Precision Time Protocol Interface
2.16. Precision Time Protocol Interface x
2.16.1. PTP Clock Interface 2.16.2. Time-of-Day Interface 2.16.3. TX 2-Step Timestamp Interface 2.16.4. TX 1-Step Timestamp Interface 2.16.5. RX Timestamp Interface 2.16.6. PTP Status Interface 2.16.7. PTP Tile Interface
4. Designing with the IP Core x
4.1. Specifying the IP Core Parameters and Options 4.2. Generated File Structure
4.1. Specifying the IP Core Parameters and Options x
4.1.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Precision Time Protocol
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Ethernet Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide

2.14. Deterministic Latency Interface

The Deterministic Latency Interface ports are available when you turn on Include Deterministic Latency Interface in FlexE mode using the IP Parameter Editor.

Use the deterministic latency interface if you want to precisely measure the latency along the TX/RX datapaths. It compares the arrival time of a known digital bit (typically the start of an alignment marker) with the arrival time of an analog pulse generated at the same point.
Figure 4. Enable Deterministic Latency Interface IP Parameter Editor
Note: You cannot enable the Deterministic Latency Interface and PTP interface at the same time.
The table below depicts the deterministic latency interface ports that are exposed to the user when the FlexE mode is turned on.
Note: When the Deterministic Latency Interface is enabled, you need to drive sync pulses to the i_tx_pcs66_am port and expect pulses from the o_rx_pcs66_am_valid port.
Table 65.  Signals of the Deterministic Latency InterfaceAll of the Deterministic Latency Interface signals are asynchronous. The width <n> in this table refers to the number of transceivers required for the Ethernet port.

Signal Name

Width

Description

o_tx_dl_async_pulse[n-1:0] <n>

Asynchronous output latency pulse from TX datapath.
o_rx_dl_async_pulse[n-1:0] <n>

Asynchronous output latency pulse from RX datapath.
i_latency_sclk[n-1:0] <n>

Asynchronous latency calibration pulse input.
i_tx_dl_measure_sel[n-1:0] <n>
Mux select signal for the TX path.
  • 0 is for the wire delay.
  • 1 is for the datapath latency.
i_rx_dl_measure_sel[n-1:0] <n>
Mux select signal for the RX path.
  • 0 is for the wire delay.
  • 1 is for the datapath latency.
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