F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 8/17/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example 5. Detailed Description for Ethernet to CPRI Design Example 6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 3.2. PMA/FEC Direct PHY Multirate Design Example: Registers
3.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
3.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 3.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
4. Detailed Description for Ethernet Multirate Design Example x
4.1. Ethernet Multirate Design Example: Functional Description 4.2. Ethernet Multirate Design Example: Registers
4.1. Ethernet Multirate Design Example: Functional Description x
4.1.1. Ethernet Multirate Design Example: Simulation Testbench 4.1.2. Ethernet Multirate Hardware Design Example
5. Detailed Description for Ethernet to CPRI Design Example x
5.1. Ethernet to CPRI Design Example: Functional Description 5.2. Ethernet to CPRI Design Example: Registers
5.1. Ethernet to CPRI Design Example: Functional Description x
5.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example
5. Detailed Description for Ethernet to CPRI Design Example
6. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
7. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

3.2. PMA/FEC Direct PHY Multirate Design Example: Registers

Table 10.  Address Map for 50G-1 Base Variant
Address Range (Byte Addressing) Maps to
0x00000000 - 0x0001FFFF F-Tile PMA/FEC Direct PHY Intel® FPGA IP Soft CSR Registers and F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers.
Note: For F-Tile PMA/FEC Direct PHY Soft CSR registers, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map. The register addresses in the reference document use byte addressing format instead of word addressing format.
Note: For F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers, refer to F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP User Guide; Soft CSR Registers.
0x00800000 - 0x008FFFFF FGT and FHT PMA Registers
0x10000000 - 0x100003FF Dynamic Reconfiguration Controller Registers.
Note: For a complete list and detailed information about the Dynamic Reconfiguration control and status registers, refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide; Configuration Registers.
Table 11.  Address Map for 400G-8 Base Variant
Address Range (Byte Addressing) Maps to
0x00000000 - 0x000FFFFF F-Tile PMA/FEC Direct PHY Intel® FPGA IP Soft CSR Registers and F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers.
Note: For F-Tile PMA/FEC Direct PHY Soft CSR registers, refer to F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map. The register addresses in the reference document use byte addressing format instead of word addressing format.
Note: For F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Reconfiguration Soft CSR Registers, refer to F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP User Guide; Soft CSR Registers.
0x04000000 - 0x047FFFFF FGT and FHT PMA Registers
0x10000000 - 0x100003FF Dynamic Reconfiguration Controller Registers.
Note: For a complete list and detailed information about the Dynamic Reconfiguration control and status registers, refer to the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP User Guide; Configuration Registers.
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