5.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example
In the hardware design example, the ISSP modules control the DUT IP reset signals, dr_mode selection and shows the status signals. The hardware test scripts open service to the ISSP to read and drive the values. A JTAG master is instantiated to access the Avalon® memory-mapped interfaces. Bydefault, the internal serial loopback mode is disabled. The design requires an external loopback module to run the default hardware test script. You can enable the internal serial loopback by setting the loopback_mode parameter to 1 in theparameter.tcl file.
The hardware design example executes the dynamic reconfiguration transition process based on user selection as stated in src/parameter.tcl file and checks the DUT IP status, clear the MAC statistics before sending 16 packets, and lastly display the MAC statistics. There is a default dynamic reconfiguration transition sequence, but user can always modify the DR_TRANSITION array variable in src/parameter.tcl file.
set DR_TRANSITION(0)"24G_RSFEC" set DR_TRANSITION(1) "1x10GE"
Hardware Flow for Design Example:
A successful run displays Test <ftile_ethernet_cpri_dr_test> Passed in the System Console window.
For more information to test the design example in hardware, refer to Testing the Hardware Design Example.