F-Tile Dynamic Reconfiguration Design Example User Guide
ID
710582
Date
6/21/2022
Public
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1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
Figure 19. PMA/FEC Direct PHY Multirate Hardware Design Example Block Diagram: 50G-1 Base Variant
In the hardware design example, the ISSP modules control the DUT IP reset signals, SIP dr_mode and shows the status signals. The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interface.
The hardware design example executes the dynamic reconfiguration transition process based on user selection as stated in src/parameter.tcl file and checks the DUT IP status. There is a default dynamic reconfiguration transition sequence, but user can always modify the DR_TRANSITION array variable in src/parameter.tcl file.
DR_TRANSITION: Intended DR sequence array, size of this array variable determines the number of dynamic reconfiguration to be performed. For example, if you want to achieve the following dynamic reconfiguration sequence: 1x50G > 1x25G > 1x50G KPFEC > 1x24.33024G > 1x50G, the variables changes are:
set DR_TRANSITION(0) "1x25G"
set DR_TRANSITION(1) "1x50G KPFEC"
set DR_TRANSITION(2) "1x24.33024G"
set DR_TRANSITION(3) "1x50G