F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 4.2. PMA/FEC Direct PHY Multirate Design Example: Registers
4.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
4.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 4.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
5. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
6. Document Revision History for F-Tile Dynamic Reconfiguration Design Example User Guide

1.4. Compiling the Compilation-Only Project

To compile the compilation-only example project, follow these steps:

  1. Ensure compilation design example generation is complete.
  2. In the Intel® Quartus® Prime Pro Edition software, open the Intel® Quartus® Prime Pro Edition project:
    • For CPRI Multirate Design Example: <design_example_dir>/compilation_test_design/cpriphy_dr_ed.qpf
    • For Ethernet Multirate Design Example: <design_example_dir>/compilation_test_design/eth_dr_ed.qpf
    • For PMA/FEC Direct PHY Multirate Design Example: <design_example_dir>/compilation_test_design/dphy_dr_ed.qpf
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, reports for timing and for resource utilization are available in your Intel® Quartus® Prime Pro Edition session.
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