1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
|Intel® Quartus® Prime Design Suite 23.1|
|IP Version 19.3.2|
The Serial Digital Interface (SDI) II Intel FPGA IP design examples for Intel Agilex® 7 F-tile devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
When you generate the design example, the IP parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Note: The hardware support for the SDI II Intel FPGA IP design example for Intel Agilex® 7 F-tile devices is in preliminary status.
Figure 1. Development Stages
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