F-Tile SDI II FPGA IP Design Example User Guide

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ID 710496
Date 9/15/2023
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Document Table of Contents
Document Table of Contents x
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide 2. Design Example Detailed Description 3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design in Hardware 1.5. Design Example Parameters
1.5. Design Example Parameters x
1.5.1. Design Example Presets
2. Design Example Detailed Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signal
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme
2.3.2. Clocking Scheme x
2.3.2.1. Clocking Scheme Components
2.4. Simulation x
2.4.1. Testbench Components 2.4.2. Test Description
2.5. Hardware Testing x
2.5.1. Parallel loopback 2.5.2. Serial loopback
1. F-Tile SDI II Intel FPGA IP Design Example Quick Start Guide
2. Design Example Detailed Description
3. F-Tile SDI II Intel FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile SDI II Intel FPGA IP Design Example User Guide

1.5.1. Design Example Presets

The Parameter Editor includes four design example presets using different video standards that you can use to pre-configure the IP and target your device development kit and Nextera daughter card directly. Hover over a preset for its description.
Table 5.  Design Example Parameter Settings
Preset Parameter Settings
3G-SDI Serial Loopback
  • Under IP tab:
    • Video standard: 3G-SDI
    • Direction: Transmitter
    • Transmitter options: Insert payload ID enabled
  • Under Design Example tab:
    • Available Design Example: Serial loopback
    • Design Example Options: Dynamic Tx clock switching disabled (can be enabled)
HD-SDI Serial Loopback
  • Under IP tab:
    • Video standard: HD-SDI
    • Direction: Transmitter
  • Under Design Example tab:
    • Available Design Example: Serial loopback
    • Design Example Options: Dynamic Tx clock switching disabled (can be enabled)
Multi Rate Parallel Loopback with VCXO
  • Under IP tab:
    • Video standard: Multi Rate (up to 12G-SDI)
    • Direction: Receiver
    • Receiver options: CRC error output
  • Under Design Example tab:
    • Available Design Example: Parallel loopback with external VCXO
Triple Rate Parallel Loopback without VCXO
  • Under IP tab:
    • Video standard: Triple Rate (up to 3G-SDI)
    • Direction: Receiver
    • Receiver options: CRC error output
  • Under Design Example tab:
    • Available Design Example: Parallel loopback without external VCXO
Figure 12. Location of the Design Example Presets in the Parameter Editor UI
Level Two Title