F-Tile SDI II FPGA IP Design Example User Guide

ID 710496
Date 9/15/2023
Public

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1.5. Design Example Parameters

Table 4.  Parameters available in Design Example tab
Parameter Value Description
Select Design
  • Parallel loopback with external VCXO
  • Parallel loopback without external VCXO
  • Serial loopback

Select a design example for generation.

  • Parallel loopback with external VCXO: Parallel loopback design with an external VCXO to synchronize the clock between RX and TX.
    Note: In the Intel Agilex® 7 device family, the FVH sync output signals from RX core is not accurate enough to clock the external VCXO in SD-SDI mode for genlocking purpose. As a workaround, Intel recommends using an external sync separator to generate this signal to the external VCXO. Alternatively, use parallel loopback without VCXO design example.
  • Parallel loopback without external VCXO: Parallel loopback design utilizes internal PLL on Intel® FPGA IP to synchronize the clock between RX and TX. The TX PLL operates in fractional mode with 141 MHz as its reference clock frequency.
  • Serial loopback: An internal video pattern generator generates along with TX and transmits to RX. This design allows simple demonstration when you do not have a video source available.
    Note: Serial loopback design is not supported when you select AXIS-VVP Full active video data protocol in the IP tab.
Dynamic TX clock Switching
  • Off
  • TX PLL reference clock switching

Turn on this option to allow dynamic switching between 1 and 1/1.001 data rates. Tx reference clock switching requires two reference clocks for TX PLL.

Note: TX PLL reference clock switching is only available when you select Serial Loopback design.
Simulation On / Off Turn on this option to generate necessary files for simulation testbench.
Note: Simulation is not supported when you select AXIS-VVP Full active video data protocol in the IP tab.
Synthesis On

Turn on this option to generate necessary files for Intel® Quartus® Prime compilation and hardware demo.

This option is greyed out and always set to Enabled. This is because synthesis files are still required to run Support-Logic Generation stage in Intel® Quartus® Prime to generate the transceiver tile’s files which are essential to run simulation as well.

Generate File Format
  • Verilog
  • VHDL
Select the HDL format for generated design example fileset. Note that the HDL format only affects the generated top level IP files. All the other files, for example testbenches and top level files for hardware demo are in Verilog.
Select Daughter card
  • Nextera VIDIO 12G-SDI FMC card
Select the daughter card for the targeted design example. This option is greyed out as only Nextera VIDIO 12G-SDI FMC card is supported in this design example.
Select Board
  • No Development Kit
  • Agilex 7 I-Series SOC Development Kit
  • Custom Development Kit
Select the board for the targeted design example.
  • No Development Kit: This option excludes hardware aspects for the design example. All the pin assignments are set to virtual pins.
  • Agilex 7 I-Series SOC Development Kit: If selected, the Intel® Quartus® Prime software automatically assigns the AGIB027R31B1E1VAA device to the project. The design example sets all the pin assignments appropriate for the device. To select a different device that matches your development kit revision, turn on Change Target Device.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA device. You may need to set the pin assignment yourself.
Change Target Device On / Off If you select Agilex 7 I-Series SOC Development Kit in Select Board, turn on this option to select a device other than AGIB027R31B1E1VAA. Then, from the main menu, click Assignments > Device, and select a different supported device.