AN 964: Signal Tap Tutorial for Intel® Agilex™ Partial Reconfiguration Design
ID
710463
Date
2/25/2022
Public
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2.1. Step 1: Getting Started
2.2. Step 2: Preparing the Base Revision
2.3. Step 3: Preparing the Implementation Revisions for Debugging
2.4. Step 4: Configuring Signal Tap Logic Analyzer
2.5. Step 5: Generating Programming Files
2.6. Step 6: Programming the FPGA Device
2.7. Step 7: Performing Data Acquisition
2.4.3. Setting Trigger Conditions
Direct the Signal Tap Logic Analyzer to record data only after u_blinking_led|led_three_on or u_blinking_led|led_two_on does a rising edge transition:
To set trigger conditions for the current revision:
- In the Setup tab of the Signal Tap Logic Analyzer window, turn on the box under the Trigger Condition column
- Open the drop-down menu and select Basic OR.
- For u_blinking_led|led_three_on and u_blinking_led|led_two_on, turn on Trigger Enable and select Rising Edge as the trigger type.
- For all the other signals, turn off Trigger Enable.
Figure 25. Trigger Conditions
Defining trigger conditions completes the Signal Tap instance configuration.
Save your changes before you continue to compiling the design.