F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Design Limitation (AXI/CV)
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer) 3.3.3. HDMI 2.1 RX-Only Retransmit Design Block Diagram 3.3.4. HDMI 2.1 TX-Only Retransmit Design Block Diagram
3.4. Design Parameters x
3.4.1. IP Parameters 3.4.2. Design Example Parameters
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions 3.9.2. Running the TX-Only Design 3.9.3. Running the RX-Only Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Agilex™ 7 F-Tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.9.2. Running the TX-Only Design

Before running the TX-only design, program the design, set the DIP switches, and adjust the clock settings according to the instructions in Compiling and Testing the Design.

For the TX-only design, the following video resolutions are supported:
Video Resolution Color Depth (Bits per components)
720x480p60 (Vic 2) 8
1280x720p60 (Vic 4) 8
1920x1080p60 (Vic 16) 8
3840x2160p30 (Vic 95) 8
3840x2160p60 (Vic 97) (Default) 8

The default resolution is 3840x2160p60 (Vic 97) 8 Bpc. Change the video resolution by following these steps:

  1. Modify the TPG_VIC define variable in main.c software file to configure TPG to the desired resolution.
  2. Modify the TX_MAX_FRL_RATE define variable in main.c software file to configure TPG to the desired FRL Rate (from 0 to 6).
  3. Rebuild the software and run the new .elf file as follows:
    1. Start a Nios® V Command Shell session.
    2. Change directory to /software/tx_control.
    3. Run the make. command.
    4. Download the .elf file with the following command: 
      niosv-download <project directory> / software/tx_control/tx_control.elf -g -r -i 0
    5. Start a JTAG UART terminal session with the following command: 
      juart-terminal -i 0
      This command generates output similar to the following example output: 
      CVO 3840x2160P60_MODE DS125BR820 TX = 85
DS125BR820 RX= 46
HDMI TX initialization done
Check TX hotplug:
EDID Sink format support updated:
        Sink Name          = 00980 HDMI RX
        Y444 Support       = 1
        Y422 Support       = 1
        Max TMDS char rate = 600
        SCDC present       = 1
        Max FRL rate       = 6
TX hotplug detected.
TX TMDS Clock Freq = 74250000Hz, out5_divider = 0, out6_divider = 0
Configure SI5391 OUT6 to frequency= 74250000 hz
Preamble
Configure OUTS
Configure OUT6
Configure OUTS
Post-amble
SI5391B [0x000C] = 0x00
SI53918 Locked after reconfiguration
Set TX FRL Rate = 6
HDMI TX LTS: link_training_LTS3
HDMI TX LTS: link_training_LTSP
FRL: Completed link training
software process done
Level Two Title